DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 09/02/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS(s) have been considered by the Examiner.
Response to Amendments
Entry of Amendments
Claim(s) 1 have been amended.
Objections to the Claims
Amendments made to claim(s) 1 have overcome the previous objections. Claim(s) 1 are no longer objected.
Rejections under 35 USC 102 and 103
Applicant’s amendments filed 08/28/2026 with respect to Claim(s) 1-16 have been fully considered but they are not persuasive.
As to applicant(s) argument of “Ummelmann does not disclose, teach, or suggest element 430-1 or 430-2 as a switch, and does not disclose, teach, or suggest
either element as gating a connection between a power supply and any other component”, the Examiner respectfully disagrees. MOS transistor is generally considered an electronic switch. Although, Ummelmann’s teaching identifies 430* as part of “amplification means”, however, they additionally perform switching function gated by feedback voltage (see col. 5 lines 10-12 :- transistors controlled by voltage Vfb) and whose source and drain terminals are connected to the power supply and opamp input respectively. Therefore, Examiner believes Ummelmann teaches the claimed limitation.
Applicant's arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to the reference(s) and/or ground(s) being used in the current rejection.
For further details see the rejections/objections for Claim(s) 1-16 herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-7, 9-10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ummelmann et al. (US 9231520; hereinafter Ummelmann) in view of Sung et al. (US 20070183103).
Regarding claim 1, Ummelmann teaches in figure(s) 3-7 a DC arc signal generation circuit, comprising:
a first power supply (VDD; fig. 4), a first switch unit (430*), and a Wien bridge oscillator circuit (420);
the Wien bridge oscillator circuit (420) comprises an operational amplifier (440,410);
wherein, the first power supply is electrically connected to a positive input terminal and a power supply terminal of the operational amplifier (terminals of 410) respectively through the first switch unit (mos switch 430* controlled by vfb* implies switching function); and
the Wien bridge oscillator circuit is configured to output a detection signal (col. 6 lines 42-45 :- amplitude detector 460 may set weighting factor k correspondingly and thus may control the amplitude of Vosc to a desired range) in response to turn-on of the first switch unit.
Ummelmann does not teach explicitly DC arc detection signal.
However, Sung teaches in figure(s) 1-7 DC arc detection signal (215, 110; fig. 1; para. 15 - Direct Current (DC) conversion unit … arc detection unit outputting a corresponding arc detection signal).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ummelmann by having DC arc detection signal as taught by Sung in order to provide some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention as evidenced by "a circuit for preventing a malfunction of an arc fault detection device for determining whether an arc fault occurs through a low-current route or a high-current route" (abstract of Sung).
Regarding claim 2, Ummelmann teaches in figure(s) 3-7 the DC arc signal generation circuit according to claim 1, wherein, the DC arc signal generation circuit further comprises a controller (470,510; fig. 5), and the first switch unit comprises a first resistor (rds) and a first switch (430); a first terminal of the first resistor is connected to the controller and a first terminal (drain of 430) of the first switch respectively, and a second terminal (vdd, supply of 500) of the first resistor is connected to the first power supply and a second terminal (source of 430) of the first switch respectively, and a third terminal (gate of 430) of the first switch is connected to the Wien bridge oscillator circuit (420).
Regarding claim 3, Ummelmann teaches in figure(s) 3-7 the DC arc signal generation circuit according to claim 1, wherein, the first switch unit comprises a key switch (430), a first terminal of the key switch is connected to the first power supply (vdd), and a second terminal of the key switch is connected to the Wien bridge oscillator circuit (420).
Regarding claim 5, Ummelmann teaches in figure(s) 3-7 the DC arc signal generation circuit according to claim 1, wherein the Wien bridge oscillator circuit comprises a frequency selection network (510, R2,C2; fig. 5) and a second resistor (R1, R5), and the frequency selection network comprises a third resistor (R2) and a first capacitor (C2); a first terminal of the second resistor is connected to the first switch unit (430); and a second terminal of the second resistor (R1) is connected to a first terminal of the third resistor, a first terminal of the first capacitor (C2), and a positive input terminal of the operational amplifier (410) respectively; and the third resistor (R2) is connected in parallel with the first capacitor (C2), and a second terminal of the third resistor (R2) is connected to a second terminal of the first capacitor (C2) and then grounded (GND).
Regarding claim 6, Ummelmann teaches in figure(s) 3-7 the DC arc signal generation circuit according to claim 1, wherein the DC arc signal generation circuit further comprises a demultiplexer (branches of 430); and an output terminal (connections to gates of 430) of the Wien bridge oscillator circuit is connected to the demultiplexer.
Regarding claim 7, Ummelmann teaches in figure(s) 3-7 the DC arc signal generation circuit according to claim 6, wherein the DC arc signal generation circuit further comprises a current conversion branch (450); the current conversion branch comprises a second switch unit (430-1), and the output terminal of the Wien bridge oscillator circuit (420) is electrically connected to the second switch unit; and the current conversion branch is configured to output a current signal in response to turn-on of the second switch unit (@gate of 430-1).
Regarding claim 9, Ummelmann in view of Sung teaches a DC arc detection device, comprising a detection circuit (460; figs. 4-5 of Ummelmann; 215, 110; fig. 1 of Sung) and the DC arc signal generation circuit (circuit of figs. 4-5 of Ummelmann and fig. 1 of Sung) according to claim 6; the DC arc signal generation circuit is connected to the detection circuit; and the detection circuit is configured to detect DC arc (215, 110; fig. 1 of Sung; para. 15 - Direct Current (DC) conversion unit … arc detection unit outputting a corresponding arc detection signal) in response to an electrical signal output by the DC arc signal generation circuit.
Regarding claim 10, Ummelmann teaches in figure(s) 3-7 the DC arc detection device according to claim 9, wherein the DC arc signal generation circuit further comprises a current conversion branch (450); the current conversion branch comprises a second switch unit (430-1), and the output terminal of the Wien bridge oscillator circuit (420) is electrically connected to the second switch unit; and the current conversion branch is configured to output a current signal in response to turn-on of the second switch unit (@gate of 430-1).
Regarding claim 13, Ummelmann teaches in figure(s) 3-7 An electrical device (col. 1 line 14 - integrated circuits, i.e., ICs), comprising the DC arc detection device according to claim 9.
Regarding claim 14, Ummelmann teaches in figure(s) 3-7 the electrical device according to claim 13, wherein the DC arc signal generation circuit further comprises a current conversion branch (450); the current conversion branch comprises a second switch unit (430-1), and the output terminal of the Wien bridge oscillator circuit (420) is electrically connected to the second switch unit; and the current conversion branch is configured to output a current signal in response to turn-on of the second switch unit (@gate of 430-1).
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over ZHANG et al. (translation of CN 106199477) in view of Li et al. (translation of CN 103399236).
Regarding claim 1, ZHANG teaches in figure(s) 1-3 a DC arc signal generation circuit (abs. - AFIC and photovoltaic power generating system) , comprising:
a first power supply (VCC; fig. 3), a first switch unit (111,Q1), and a Bridge circuit (RC bridge circuit of fig. 3);
the Bridge circuit comprises an operational amplifier (output opamp U1 of fig. 3);
wherein, the first power supply (Vcc) is electrically connected to a positive input terminal (+/U1) and a power supply terminal (Vcc) of the operational amplifier (U1) respectively through the first switch unit (111,Q1); and
the Bridge circuit is configured to output a DC arc detection signal (@U1; pg. 9 - DC component of the arc noise signal C1 can work in normal state) in response to turn-on of the first switch unit (pg. 9 - first switch 111 can make… so that Q1 of the source electrode and the drain electrode can be conducted).
ZHANG does not teach explicitly Wien bridge oscillator.
However, Li teaches in figure(s) 1-2 Wien bridge oscillator (paras. 6,12 - Wien Bridge circuit … sine wave oscillating circuit; fig. 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of ZHANG by having Wien bridge oscillator as taught by Li in order to provide some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention as evidenced by "testing circuit of residual current protection of the residual current protecting device… an electric test signal by sine-wave oscillation circuit analogue output drain, high circuit reliability" (abstract of Li).
Claim(s) 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ummelmann in view of Sung, and further in view of Nasu et al. (US 20120139633).
Regarding claim(s) 12 and 16, Ummelmann in view of Sung teaches the DC arc detection device according to claim 10 and the electrical device according to claim 14, respectively.
Ummelmann does not teach explicitly wherein the detection circuit comprises a signal amplifying unit, a filtering unit and a signal processing unit; the signal amplifying unit is connected to the demultiplexer, and/or the signal amplifying unit is connected to the current conversion branch; and the filtering unit is connected to the signal amplifying unit, and the signal processing unit is connected to the filtering unit.
However, Nasu teaches in figure(s) 8-13 wherein the detection circuit comprises a signal amplifying unit, a filtering unit (30; fig. 12) and a signal processing unit (dsp 7; fig. 13); the signal amplifying unit is connected to the demultiplexer (312; fig. 8), and/or the signal amplifying unit is connected to the current conversion branch; and the filtering unit is connected to the signal amplifying unit, and the signal processing unit is connected to the filtering unit.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ummelmann by having wherein the detection circuit comprises a signal amplifying unit, a filtering unit and a signal processing unit; the signal amplifying unit is connected to the demultiplexer, and/or the signal amplifying unit is connected to the current conversion branch; and the filtering unit is connected to the signal amplifying unit, and the signal processing unit is connected to the filtering unit as taught by Nasu in order to provide "a source follower configured to receive an output of the attenuator, and an amplifying unit configured to perform a filtering process on an output of the source follower, and then amplify the output of the source follower with a variable gain." (abstract).
Allowable Subject Matter
Claim(s) 4, 8, 11 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior arts of record do not fairly teach or suggest “wherein the DC arc signal generation circuit further comprises a controller; the first switch unit comprises a first resistor, a first switch, a key switch and an OR gate; a first terminal of the first resistor is connected to the controller and a first terminal of the first switch respectively, and a second terminal of the first resistor is connected to the first power supply and a second terminal of the first switch respectively, and a third terminal of the first switch is connected to a second input terminal of the OR gate; a first terminal of the key switch is connected to the first power supply, and a second terminal of the key switch is connected to a first input terminal of the OR gate; an output terminal of the OR gate is connected to the Wien bridge oscillator circuit” including all of the limitations of the base claim and any intervening claims.
Regarding claim(s) 8, 11 and 15, the prior arts of record do not fairly teach or suggest “wherein the current conversion branch comprises a second switch, a fourth resistor, a fifth resistor, a current transformer and a second power supply; the current conversion branch provides a first current path; the second switch, the fourth resistor, and the second power supply are part of the first current path; and the first current path passes through the current transformer; and a first terminal of the fifth resistor is connected to an output terminal of the operational amplifier and a control terminal of the second switch respectively, and a second terminal of the second switch is connected to a second terminal of the fifth resistor and then grounded, a first terminal of the second switch is connected to a first terminal of the fourth resistor, a second terminal of the fourth resistor is connected to a positive electrode of the second power supply, a negative electrode of the second power supply is connected to the second terminal of the second switch” including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment and/or submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 09/02/2026 necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a), § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JUDY NGUYEN can be reached on 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/Primary Examiner, Art Unit 2858
