DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a detection unit” and “a feedback-control unit” in claims 1 and 13 (see also Applicant’s figure 2: 60 and 50).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 6-8, 13, 14, 16, 19 and 20 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Cronin et al. U.S. Patent Publication No. 2018/0040276 (hereinafter Cronin).
Consider claim 1, Cronin teaches an electronic device ([0046], display), comprising a substrate (circuit substrate for 1 in figure 4), a plurality of light-emitting components and a plurality of driving circuits (Figure 4, 1 and 2. [0002], LEDs); wherein the light-emitting components are arranged on the substrate (Figure 4, 2), the driving circuits electrically connect the light-emitting components and correspond to the light-emitting components respectively (Figure 4, 1 and 2); wherein one or ones of the light-emitting components emits lights in response to a driving signal (Figure 4, 2); and wherein the driving circuit includes: a transistor including an input terminal and two output terminals, wherein the transistor delivers the driving signal to a corresponding one or corresponding ones of the light-emitting components by one of the two output terminals (Figure 4, 8 and 2); wherein the transistor defines a characteristic curve in which the characteristic curve is defined by one output current versus a voltage gap between the two output terminals (IV curve for a transistor, [0047], FET), and the characteristic curve defines an operation region and an output conductance within the operation region (linear and saturation regions for a FET (see for example, Shigeta et al. U.S. Patent Publication No. 2018/0293929: figure 3a, linear region and saturation region)), wherein the output conductance defines an absolute value of a ratio of an output current change to a voltage gap change (conductance in the linear and saturation regions for a FET); wherein the operation region further defines a first region and a second region, an output conductance of the first region is greater than an output conductance of the second region (conductance of linear region is greater than conductance of saturation region since variation of current in saturation is constant (see for example, Shigeta’s figure 3a)), and the transistor is operated within the first region ([0048], linear regime); a detecting unit delivering a detection output in response to a corresponding one of the light-emitting components (Figure 4, 11); and a feedback-control unit directing the transistor in response to the detection output to regulate the driving signal (Figure 4 and [0049-0050], 10-11 and 8).
Consider claim 2, Cronin teaches all the limitations of claim 1. In addition, Cronin teaches wherein the transistor is a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), or a field-effect transistor (FET) ([0047], FET).
Consider claim 4, Cronin teaches all the limitations of claim 1. In addition, Cronin teaches wherein the transistor is a field effect transistor (FET); the input terminal is a gate, and the two output terminals are a drain and a source (Figure 4 and [0048], FET 8); the first region denotes a linear region of the FET, while the second region denotes a saturation region of the FET (Figure 4, linear and saturation regions for FET 8 (see also Shigeta’s figure 3a)).
Consider claim 6, Cronin teaches all the limitations of claim 1. In addition, Cronin teaches wherein the detecting unit detects the driving signal, which drives the corresponding one of the light-emitting components, and delivers the detection output in response thereto (Figure 4 and [0050], current monitor unit 11, drive current control unit 10 and current control transistor 8).
Consider claim 7, Cronin teaches all the limitations of claim 6. In addition, Cronin teaches wherein the detecting unit (Figure 4, elements 10-11) includes a resistor electrically connecting with the corresponding one of the light-emitting components in serial (Figure 4, resistor 9 and LED 2), and the feedback-control unit (Figure 4, 8-11) directing the transistor based on a voltage drop across the resistor ([0049], voltage is dropped across the current sensing resistor (see also [0050]).
Consider claim 8, Cronin teaches all the limitations of claim 1. In addition, Cronin teaches wherein the driving circuits are at least partially formed on the substrate (substrate for Figure 4, 1).
Consider claim 13, Cronin teaches an electronic circuitry (Figure 4, 1), comprising: a plurality of light-emitting components (Figure 4, 1 and 2. [0002], LEDs), each of the light-emitting components configured with lighting in response to an driving signal (Figure 4, elements 2 and 8); and a plurality of driving circuits corresponding to the light-emitting components respectively (Figure 4, elements 2 and 8); wherein the driving circuits includes: a transistor including an input terminal and two output terminals, wherein the transistor delivers the driving signal to a corresponding one or corresponding ones of the light-emitting components by one of the two output terminals (Figure 4, 8 and 2); wherein the transistor defines characteristic curve in which the characteristic curve is defined by one output current versus a voltage gap between the two output terminals (IV curve for a transistor, [0047], FET), and the characteristic curve defines an operation region and an output conductance within the operation region (linear and saturation regions for a FET (see for example, Shigeta et al. U.S. Patent Publication No. 2018/0293929: figure 3a, linear region and saturation region)), wherein the output conductance defines an absolute value of a ratio of an output current change to a voltage gap change (conductance in the linear and saturation regions for a FET); wherein the operation region further defines a first region and a second region, an output conductance of the first region is greater than an output conductance of the second region (conductance of linear region is greater than conductance of saturation region since variation of current in saturation is constant (see for example, Shigeta’s figure 3a)), and the transistor is operated within the first region ([0048], linear regime); a detecting unit delivering a detection output in response to a corresponding one of the light-emitting components (Figure 4, 11); and a feedback-control unit directing the transistor to regulate the driving signal (Figure 4 and [0049-0050], 10-11 and 8).
Consider claim 14, it includes the limitations of claim 2 and thus rejected by the same reasoning.
Consider claim 16, it includes the limitations of claim 4 and thus rejected by the same reasoning.
Consider claim 19, it includes the limitations of claim 6 and thus rejected by the same reasoning.
Consider claim 20, it includes the limitations of claim 7 and thus rejected by the same reasoning.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cronin as applied to claim 2 above, and further in view of Shigeta et al. U.S. Patent Publication No. 2018/0293929 (hereinafter Shigeta).
Consider claim 3, Cronin teaches all the limitations of claim 2.
Cronin does not appear to specifically disclose wherein the FET includes types of metal-oxide-semiconductor field-effect transistor (MOSFET), metal semiconductor field effect transistor (MESFET) or thin-film transistor (TFT).
However, in a related field of endeavor, Shigeta teaches a pixel circuit of a display panel (abstract) and further teaches wherein the FET includes types of metal-oxide-semiconductor field-effect transistor (MOSFET), metal semiconductor field effect transistor (MESFET) or thin-film transistor (TFT) [0238-0239].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide TFT as taught by Shigeta since the channel of the TFT may be made of oxide or organic material as suggested in [0238].
Consider claim 9, Cronin teaches all the limitations of claim 1.
Cronin does not appear to specifically disclose each of the driving circuits is at least partially arranged upon an integrated circuit.
However, Shigeta teaches in [0229], driving module…may be implemented by…integrated chip.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide an integrated circuit for the purpose of design choices since Cronin teaches integrated or separated semiconductor ICs in [0229]. Furthermore, integration should reduce space or improve compactness.
Consider claim 15, it includes the limitations of claim 3 and thus rejected by the same reasoning.
Claim(s) 5, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cronin as applied to claim 1 above, and further in view of Lee et al. U.S. Patent Publication No. 2003/0151569 (hereinafter Lee).
Consider claim 5, Cronin teaches all the limitations of claim 1.
Cronin does not appear to specifically disclose wherein the detecting unit senses the light emitted from the corresponding one of the light-emitting components and delivers the detection output in response thereto.
However, in a related field of endeavor, Lee teaches a light emitting pixel (abstract) and further teaches wherein the detecting unit senses the light emitted from the corresponding one of the light-emitting components and delivers the detection output in response thereto (Figure 2 and [0024], photodiode 34).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a light detection unit as taught by Lee with the benefit that the feedback signal detected from the photo-sensor elements can be used to provide feedback from the light detected in the display control circuit to compensate for changes or differences in light output from pixels as suggested by Lee in [0024].
Consider claim 17, it includes the limitations of claim 5 and thus rejected by the same reasoning.
Consider claim 18, Cronin and Lee teach all the limitations of claim 17. In addition, Lee teaches wherein the detecting unit includes a photo diode [0019], see motivation to combine in claim 5.
Claim(s) 10-12 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cronin as applied to claim 1 above, and further in view of Miyasaka et al. U.S. Patent Publication No. 2020/0111425 (hereinafter Miyasaka).
Consider claim 10, Cronin teach all the limitations of claim 1.
Cronin does not appear to specifically disclose wherein each of the light-emitting components defines a voltage drop thereof; the voltage gap of one of the driving-current control transistors is less than or equal to the voltage drop of a corresponding one of the light-emitting components.
However, in an related field of endeavor, Miyasaka teaches a pixel circuit in figure 9 and further teaches wherein each of the light-emitting components defines a voltage drop thereof; the voltage gap of one of the driving-current control transistors is less than or equal to the voltage drop of a corresponding one of the light-emitting components ([0126], by setting the On-resistance of the first transistor 31 and/or the fourth transistor 34 to 1/100 or less of the On-resistance of the light-emitting element 20, the light-emitting element 20 receives 99% or more of the power supply voltage, and the potential drop in both transistors 31 and 34 becomes 1% or less).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide particular voltage gap/drop as taught by Miyasaka with the benefit that since the potential drop in both transistors 31 and 34 is 1% or less, the influence of the variations in the threshold voltage of both transistors 31 and 34 on the light emission property of the light-emitting element 20 is small as suggested in [0126].
Consider claim 11, Cronin and Miyasaka teach all the limitations of claim 10. Miyasaka teaches wherein the voltage gap of one of the transistors is less than or equal to two-thirds of the voltage drop of a corresponding one of the light-emitting components [0126], see motivation to combine in claim 10.
Consider claim 12, Cronin and Miyasaka teach all the limitations of claim 10. Miyasaka teaches wherein the voltage gap of one of the driving-current control transistors is less than or equal to half of the voltage drop of a corresponding one of the light-emitting components [0126], see motivation to combine in claim 10.
Consider claim 21, it includes the limitations of claim 10 and thus rejected by the same reasoning.
Consider claim 22, it includes the limitations of claim 11 and thus rejected by the same reasoning.
Consider claim 23, it includes the limitations of claim 12 and thus rejected by the same reasoning.
Response to Arguments
Applicant's arguments filed 10/28/2025 have been fully considered but they are not persuasive.
On page 9, Applicant argues that “In Cronin, paragraph [0048] of the specification discloses that “the gate of the transistor is connected to a drive current control unit 10 which is arranged to apply a voltage to the gate terminal which is below the threshold voltage of the transistor 8 for operating the transistor in ...”. This disclosure would suggest to a person of ordinary skill in the art that transistor 8 is a P-channel MOSFET. However, as shown in FIG. 4 corresponding to paragraph [0048], the connection of transistor 8 within the circuit, namely “the drain and source terminals of the current control transistor are connected to the cathode of the LED and the current sensing resistor 9, respectively”, together with the sequence of electrical connections in FIG. 4 (Voltage source (5) — LED (2) — FET (8) > ground terminal (7)) would instead lead one of ordinary skill in the art to conclude that transistor 8 is an N-channel MOSFET. In other words, Cronin presents a clear inconsistency between the textual description and the circuit diagram, which constitutes an apparent error”. The Office respectfully disagrees for the following reasons.
First, claim 1 does not exclude a type of transistor. In fact, claims 2-3 suggest BJT, IGBT, FET, MOSFET, MESFET or TFT. Second, Cronin teaches in [0048], transistor is connected to a drive current control unit 10 which is arranged to apply a voltage to the gate terminal which us below the threshold voltage of the transistor 8 for operating the transistor in the linear/Ohmic regime whereby the conductivity (drain current) of the transistor is variable according to the drain-to-source voltage drop across the transistor (i.e. in the manner of a variable resistor). Examiner considers that the principle for operating the transistor in the linear regime is applicable to FETs since Cronin suggests FET in this case in [0048]. Thus, one ordinary skill in the art would understand the concept of operating a FET in linear regime based on Cronin [0048-0049].
On page 10, Applicant argues that “Shigeta, however, expressly excludes operation of the driving transistor in the linear region, and therefore provides a teaching away from the claimed invention.” The Office respectfully disagrees for the following reasons.
Cronin teaches operating the transistor in the linear regime in [0048]. Shigeta teaches in [0069], NMOSFET 125-1 may operate in a linear region or in a saturation region. In addition, Examine is using Shigeta for the purpose of showing a known IV curve since Cronin teaches the linear regime in [0048]. Consequently, these arguments have been considered but they are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO W FLORES whose telephone number is (571)272-5512. The examiner can normally be reached Monday-Friday, 7am-4pm, EST.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621