DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2023/0139929).
Regarding claim 1, Xie teaches (FIG. 15A):
An integrated circuit device comprising:
a pair of fin-type active regions (D1/D2) spaced apart from each other in a second horizontal direction intersecting a first horizontal direction, wherein the pair of fin-type active regions protrude in a vertical direction that is perpendicular to the first horizontal direction from a backside insulation structure (FIG. 15A) and extend longitudinally in the first horizontal direction;
a device isolation layer (12) on opposing sidewalls of each of the pair of fin-type active regions;
a pair of source/drain regions (26) on the pair of fin-type active regions;
an interlayer insulation layer (28) on the pair of source/drain regions and the device isolation layer;
a via power rail (VIA) extending longitudinally in the first horizontal direction between the pair of fin-type active regions and extending through the interlayer insulation layer and the device isolation layer in the vertical direction;
a pair of source/drain contacts (46A/C) arranged in the second horizontal direction with the via power rail therebetween to contact the pair of source/drain regions;
a contact-merged bridge on and electrically connected to the via power rail and a first source/drain contact of the pair of source/drain contacts (46C);
a contact isolation insulation layer (34) on the via power rail and a second source/drain contact of the pair of source/drain contacts;
a via structure on the second source/drain contact ([0085]); and
a power rail wiring (56) extending through the backside insulation structure in the vertical direction and contacting the via power rail, wherein the first source/drain contact and the contact-merged bridge have a unitary structure that is free of a boundary surface therebetween (FIG. 15A).
Regarding claim 2, Xie teaches (FIG. 15A):
The integrated circuit device of claim 1, wherein an angle between a bottom surface and a sidewall of the contact-merged bridge is acute, and the bottom surface of the contact-merged bridge is on an upper surface of the via power rail, wherein an angle between a bottom surface and a sidewall of the via structure is obtuse, and the bottom surface of the via structure is on an upper surface of the second source/drain contact, and wherein an angle between a bottom surface and an outer sidewall of each of the pair of source/drain contacts is obtuse, and the bottom surface of each of the pair of source/drain contacts is on a respective upper surface of the pair of source/drain regions.
Regarding claim 3, Xie teaches:
The integrated circuit device of claim 2, further comprising: a rail insulation layer (28) on opposing sidewalls of the via power rail, wherein an inner sidewall of the first source/drain contact, which faces the second source/drain contact, contacts the rail insulation layer.
Regarding claim 4, Xie teaches (FIG. 15A):
The integrated circuit device of claim 3, wherein the upper surface of the via power rail, an upper surface of the rail insulation layer, and the upper surface of the second source/drain contact are coplanar.
Regarding claim 5, Xie teaches (FIG. 15A):
The integrated circuit device of claim 4, wherein, in a cross-sectional view, the contact-merged bridge has a trapezoid shape, and the bottom surface of the contact-merged bridge contacts the upper surface of the via power rail and the upper surface of the rail insulation layer.
Regarding claim 6, Xie teaches (FIG. 15A):
The integrated circuit device of claim 1, wherein a portion of a sidewall of the via power rail contacts the contact isolation insulation layer, and wherein an inner sidewall of the second source/drain contact, which faces the first source/drain contact, contacts the contact isolation insulation layer.
Regarding claim 7, Xie teaches (FIG. 15A):
The integrated circuit device of claim 6, wherein the contact isolation insulation layer and the contact-merged bridge are spaced apart from each other in the second horizontal direction.
Regarding claim 8, Xie teaches (FIG. 15A):
The integrated circuit device of claim 1, wherein the first source/drain contact and the via power rail do not directly contact each other at respective sidewalls and are electrically connected to each other by the contact-merged bridge at an upper surface of the via power rail.
Regarding claim 9, Xie teaches (FIG. 15A):
The integrated circuit device of claim 1, further comprising: a gate electrode (24) extending longitudinally in the second horizontal direction on the pair of fin-type active regions; and a gate capping layer on the gate electrode, wherein a bottom surface of the contact-merged bridge is spaced apart from an upper surface of the gate electrode in the vertical direction.
Regarding claim 10, Xie teaches ([0030] – [0031]):
The integrated circuit device of claim 9, further comprising a pair of nanosheet stacks between the pair of fin-type active regions and the gate electrode, wherein, in a plan view, the contact-merged bridge does not overlap the pair of nanosheet stacks.
Regarding claim 11, Xie teaches (FIG. 15A, [0030] – [0031]):
An integrated circuit device comprising:
an upper backside insulation structure including a protrusion portion and a lower backside insulation structure on a lower surface of the upper backside insulation structure opposite the protrusion portion (FIG. 15A);
a pair of fin-type active regions (D1/D2) on the protrusion portion of the upper backside insulation structure and extending longitudinally in a first horizontal direction;
a device isolation layer (12) on opposing sidewalls of each of the pair of fin-type active regions;
a pair of nanosheet stacks ([0030] – [0031]) on first portions of the pair of fin-type active regions;
a gate electrode (24) extending longitudinally on the pair of fin-type active regions to intersect with the pair of fin-type active regions and extending on the pair of nanosheet stacks;
a pair of source/drain regions (26) on second portions of the pair of fin-type active regions;
an interlayer insulation layer (28) on the pair of source/drain regions and the device isolation layer;
a via power rail (VIA) extending longitudinally in the first horizontal direction between the pair of fin-type active regions and extending through the interlayer insulation layer and the device isolation layer in a vertical direction that is perpendicular to the first horizontal direction;
a pair of source/drain contacts (46A/C) spaced apart from each other with the via power rail therebetween to contact the pair of source/drain regions;
a contact bridge on the via power rail and a first source/drain contact of the pair of source/drain contacts (46C);
a via structure ([0085]) on a second source/drain contact of the pair of source/drain contacts; and
a power rail wiring extending through the upper backside insulation structure and the lower backside insulation structure in the vertical direction and contacting the via power rail, wherein an angle between a bottom surface and a sidewall of the contact bridge is acute, the bottom surface of the contact bridge being on an upper surface of the via power rail (FIG. 15A), and wherein an angle between a bottom surface and a sidewall of the via structure is obtuse, the bottom surface of the via structure being on an upper surface of the second source/drain contact.
Regarding claim 12, Xie teaches (FIG. 15A, [0030] – [0031]):
The integrated circuit device of claim 11, wherein the first source/drain contact and the contact bridge have a unitary structure that is free of a boundary surface therebetween.
Regarding claim 13, Xie teaches (FIG. 15A):
The integrated circuit device of claim 11, wherein the first source/drain contact and the contact bridge comprise different structures with a boundary surface therebetween.
Regarding claim 14, Xie teaches (FIG. 15A):
The integrated circuit device of claim 11, wherein a thickness of the contact bridge in the vertical direction is less than a thickness of the via structure in the vertical direction.
Regarding claim 15, Xie teaches (FIG. 15A):
The integrated circuit device of claim 11, wherein a thickness of the contact bridge in the vertical direction is substantially equal to a thickness of the via structure in the vertical direction.
Regarding claim 16, Xie teaches (FIG. 2 – 15):
A method of manufacturing an integrated circuit device, the method comprising:
forming a pair of fin-type active regions (D1/D2) spaced apart from each other in a second horizontal direction intersecting a first horizontal direction, wherein the pair of fin-type active regions protrude in a vertical direction that is perpendicular to the first horizontal direction and extend longitudinally in the first horizontal direction, on a substrate;
forming a device isolation layer (12) on opposing sidewalls of each of the pair of fin-type active regions;
forming a pair of source/drain regions (26) on the pair of fin-type active regions;
forming an interlayer insulation layer (28) on the pair of source/drain regions and the device isolation layer;
forming a via power rail (VIA) extending longitudinally in the first horizontal direction between the pair of fin-type active regions and extending through the interlayer insulation layer and the device isolation layer in the vertical direction;
etching a portion of each of the pair of source/drain regions and a portion of the interlayer insulation layer therebetween to form a contact preliminary hole;
forming a contact material layer (46) in the contact preliminary hole and on an upper surface of the interlayer insulation layer;
patterning the contact material layer to simultaneously form a pair of source/drain contacts spaced apart from each other in the second horizontal direction with the via power rail therebetween and a contact-merged bridge contacting at least a portion of an upper surface of the via power rail (FIG. 12B);
forming an upper insulation layer (50) on the contact-merged bridge and the interlayer insulation layer;
forming a via structure ([0085]) extending through the upper insulation layer in the vertical direction;
removing the substrate to form a backside insulation structure in a region from which the substrate is removed (FIG. 15A); and
forming a power rail wiring (56) which extends through the backside insulation structure in the vertical direction and contacts the via power rail.
Regarding claim 17, Xie teaches (FIG. 2 – 15):
The method of claim 16, wherein a first source/drain contact of the pair of source/drain contacts and the contact-merged bridge have a unitary structure that is free of a boundary surface therebetween.
Regarding claim 18, Xie teaches (FIG. 2 – 15):
The method of claim 17, wherein, in the forming of the via power rail, a rail insulation layer (28) is formed on opposing sidewalls of the via power rail, and an inner sidewall of the first source/drain contact is formed to contact the rail insulation layer.
Regarding claim 19, Xie teaches (FIG. 2 – 15):
The method of claim 18, wherein the first source/drain contact and the via power rail do not directly contact each other at respective sidewalls and are electrically connected with each other by the contact-merged bridge at the upper surface of the via power rail.
Regarding claim 20, Xie teaches (FIG. 2 – 15):
The method of claim 16, wherein an angle between a bottom surface and a sidewall of the contact-merged bridge is acute, and the bottom surface of the contact-merged bridge is on the upper surface of the via power rail, wherein an angle between a bottom surface and a sidewall of the via structure is obtuse, and the bottom surface of the via structure is on an upper surface of a second source/drain contact of the pair of source/drain contacts, and wherein an angle between a bottom surface and an outer sidewall of each of the pair of source/drain contacts is obtuse and the bottom surface of each of the pair of source/drain contacts is on a respective upper surface of the pair of source/drain regions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Madonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 2898
