DETAILED ACTION
Applicant’s amendment, filed 06/25/2026, for application number 18/896,019 has been received and entered into record. Claims 1, 4, 8, 15, and 18 have been amended, and no claims have been cancelled or newly added. Therefore, Claims 1-20 are presented for examination. The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed on 06/25/2026 with respect to the claims have been considered but are moot due to the rejection based on the references cited below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-5, 15-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over GE, US 2022/0398024 A1 (as listed in the IDS), in view of VILLA et al., US 2010/0306446 A1, and further in view of KIM, US 2024/0281158 A1.
Regarding Claim 1, GE discloses:
A host device comprising: one or more components configured to: detect a background operation status associated with a memory device (Fig. 4 illustrates a host device 405 and components 410-430; [0047] discloses the host may identify (i.e. detect) a state of maintenance operations (i.e. background operation status) of the non-volatile memory (i.e. memory device),
Transmit, to the memory device, a power down command in accordance with a timeout associated with the background operation ([0052] discloses initiating a timer based on a command, where a duration of the timer may be set based on the state of the maintenance operations being performed; the host issues (i.e. transmits) a hibernate command (i.e. power down command) with the expiration of the timer (i.e. timeout associated with the background operation)).
However, GE does not explicitly disclose transmitting, to the memory device and based at least in part on the background operation status, a command to disable a background operation with the memory device; receiving from the memory device, a response; and instructing, based at least in part on the response, one or more resources associated with the memory device to enter into a low power mode state or an off state.
In the analogous art of power management, VILLA teaches transmitting, to the memory device and based at least in part on the background operation status, a command to disable a background operation with the memory device (Fig. 4 illustrates issuing a command 404, based on checking if the memory device is performing an operation 408 (i.e. background operation status) to safely suspend (i.e. disable) the background operation 414); receiving from the memory device, a response (receiving memory acknowledgement (i.e. response) from the memory device 412); and instructing, based at least in part on the response, one or more resources associated with the memory device to enter into a low power mode state or an off state (removal of power for the memory device 418 based on the memory acknowledgement 412, causing the memory device and resources within it to enter an off state),
an amount of time for the timeout associated with the background operation that is currently ongoing ([0022] teaches if the memory device is performing an operation, then the status register unit can be accessed to determine when the operation has been completed or suspended. The method includes receiving a memory acknowledgement at the host controller from the memory device in response to the controlled power off command or waiting a certain time period prior to safely suspending the background operation (i.e. timeout for the background operation) or completing the background operation at block 412 (i.e. waiting a duration of time before the ongoing background operation is timed out)).
Accordingly, it would have been obvious to a person having ordinary skill in the art having the teachings of GE and VILLA before him before the effective filing date of the invention, to incorporate VILLA’s disablement of background operations and entering an off state based on a response, with GE’s host device detecting a state of maintenance operations before a hibernate command in order to enhance memory reliability and data integrity (VILLA [0010]).
However, the combination of GE and VILLA do not explicitly disclose wherein an amount of time for the timeout associated with the background operation is based on a specific type of background operation.
In the analogous art of power management, KIM teaches wherein an amount of time for the timeout associated with the background operation is based on a specific type of background operation ([0068] teaches in response to receiving the standby indication of 310, the memory system 110-b may determine a duration to delay entry into the standby mode (i.e. amount of time for the timeout), which may be a duration associated with performing at least a subset of the background operations determined at 305 (e.g., all of the operations determined at 305, fewer than all of the background operations determined at 305) (i.e. the amount of time for the timeout is associated with the background operations). In some cases, the duration may be determined at 315 based on a type of the background operations determined at 305. For example, the memory system 110-b may determine the duration at 315 based on which of the background operations determined at 305 are to be performed (e.g., relatively high-priority media management operations), or a status of the memory system 110-b (e.g., a maintenance status, a health status), such that the memory system 110-b may use characteristics (e.g., level of importance, priority) of the background operations, among other evaluations to determine the duration (i.e. the amount of time for the timeout is based on the type of background operation)).
Accordingly, it would have been obvious to a person having ordinary skill in the art having the teachings of GE, VILLA, and KIM before him before the effective filing date of the invention, to incorporate KIM’s duration of delayed entry into standby based on the type of background operation, with GE and VILLA’s host device in order to support an improved balance between reduced power consumption and management of memory system maintenance (KIM [0011]).
Regarding Claim 2, GE, VILLA, and KIM disclose the host device of Claim 1. GE further discloses transmitting the power down command after waiting for the timeout associated with the background operation ([0052] teaches issuing (i.e. transmitting) a hibernate command (i.e. power down command) as a result from the timer expiring, the timer being based on the state of the maintenance operations).
Regarding Claim 4, GE, VILLA, and KIM disclose the host device of claim 1. GE further discloses transmitting the power down command without the command when the background operation status indicates no ongoing background operation at the memory device ([0038] teaches issuing (i.e. transmitting) a hibernate command (i.e. power down command) when the memory device is idle (i.e. background operation status indicates no ongoing background operation at the memory device)).
Regarding Claim 5, GE, VILLA, and KIM disclose the host device of claim 1. GE further discloses wherein the power down command is to cause the memory device to enter into one of: a power down mode, a sleep mode, or a deep sleep mode ([0010] teaches a hibernate command (i.e. power down command) is to cause the memory device to enter the lower power mode (i.e. power down mode)).
Regarding Claim 15, GE discloses a method (using host 405 of Fig. 4). The remainder of Claim 15 recites limitations similar to those of Claim 1, and is rejected accordingly.
Regarding Claim 16, GE, VILLA, and KIM disclose the method of Claim 15. Claims 16 and 18 recite limitations similar to those of Claims 2 and 4, respectively, and are rejected accordingly.
Claims 3, 6-7, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over GE, in view of VILLA, in view of KIM, and further in view of SHIN et al., US 2020/0401333 A1.
Regarding Claim 3, GE, VILLA, and KIM disclose the host device of claim 1.
However, the combination of GE, VILLA, and KIM do not explicitly disclose wherein the one or more resources includes one or more power rails or one or more clocks associated with the memory device.
In the analogous art of a UFS device power management, SHIN teaches wherein the one or more resources includes one or more power rails or one or more clocks associated with the memory device (Fig. 1 illustrates power rails VCC 132a, VCCQ2 132b, and VCCQ 132c associated with the memory device 130).
Accordingly, it would have been obvious to a person having ordinary skill in the art having the teachings of GE, VILLA, KIM, and SHIN before him before the effective filing date of the invention, to incorporate SHIN’s power rails in a UFS device with GE, VILLA, and KIM’s host device transitioning to low power states to reduce power consumption in low power modes (SHIN [0008]).
Regarding Claim 6, GE, VILLA, and KIM disclose the host device of claim 1.
However, the combination of GE, VILLA, and KIM do not explicitly teach wherein the power down command is a start stop unit (SSU) command that indicates a power condition value.
In the analogous art of a UFS device power management, SHIN teaches wherein the power down command is a start stop unit (SSU) command that indicates a power condition value ([0038] teaches a specific command shown as a START STOP UNIT command that indicates a POWER CONDITION value of “3h”).
Accordingly, it would have been obvious to a person having ordinary skill in the art of having the teachings of GE, VILLA, KIM, and SHIN before him before the effective filing date of the invention, to incorporate SHIN’s SSU command and power condition value in a UFS device with GE, VILLA, and KIM’s host device transitioning to low power states as UFS is well-suited for applications where high-performance demands are seen in conjunction with low power consumption requirements (SHIN [0003]).
Regarding Claim 7, GE, VILLA, and KIM disclose the host device of claim 1.
However, the combination of GE, VILLA, and KIM do not explicitly teach wherein the host device is a universal flash storage (UFS) host and the memory device is a UFS device.
In the analogous art of power management, SHIN teaches wherein the host device is a universal flash storage (UFS) host and the memory device is a UFS device ([0026] teaches a host device 110 and Flash memory device (e.g., UFS memory system) 130, with an interface generally designated with the reference number 120 shown between the host device 110 and Flash memory device 130).
Accordingly, it would have been obvious to a person having ordinary skill in the art of having the teachings of GE, VILLA, KIM, and SHIN before him before the effective filing date of the invention, to incorporate SHIN’s UFS host and UFS memory device with GE, VILLA, and KIM’s host device transitioning to low power states as UFS is well-suited for applications where high-performance demands are seen in conjunction with low power consumption requirements (SHIN [0003]).
Regarding Claim 17, the claim recites similar limitations as corresponding claim 3 and is rejected for similar reasons as claim 3 using similar teachings and rationale.
Regarding Claim 19, GE, VILLA, and KIM disclose the method of claim 15.
However, the combination of GE, VILLA, and KIM do not explicitly teach wherein the power down command is to cause the memory device to enter into one of: a power down mode, a sleep mode, or a deep sleep mode, and wherein the power down command is a start stop unit (SSU) command that indicates a power condition value.
In the analogous art of power management, SHIN teaches wherein the power down command is to cause the memory device to enter into one of: a power down mode, a sleep mode, or a deep sleep mode, and wherein the power down command is a start stop unit (SSU) command that indicates a power condition value ([0038] teaches a specific command (i.e. power down command) to enter the UFS power down mode (i.e. power down mode) shown a START STOP UNIT command that indicates a POWER CONDITION value of “3h”).
Accordingly, it would have been obvious to a person having ordinary skill in the art having the teachings of GE, VILLA, KIM and SHIN before him before the effective filing date of the invention, to incorporate SHIN’s SSU command and power condition value in a UFS device with GE, VILLA, and KIM’s method of transitioning to low power states as UFS is well-suited for applications where high-performance demands are seen in conjunction with low power consumption requirements (SHIN [0003]).
Regarding Claim 20, the claim recites similar limitations as corresponding claim 7 and is rejected for similar reasons as claim 7 using similar teachings and rationale.
Claims 8-10 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over GE, in view of VILLA, in view of KIM, and further in view of BALDWIN et al., US 2017/0153694 A1.
Regarding Claim 8, GE discloses:
A memory device, comprising one or more components configured to: (Fig. 5 illustrates a memory device 505 and components 510-535),
Receive, from the host device, a power down command in accordance with a timeout associated with the background operation ([0052] teaches initiating a timer based on a command, where a duration of the timer may be set based on the state of the maintenance operations being performed; the host issuing (i.e. memory device receiving) a hibernate command (i.e. power down command) with the expiration of the timer (i.e. timeout associated with the background operation),
However, GE does not explicitly disclose receiving, from a host device, a command to disable a background operation associated with the memory device; disabling the background operation based at least in part on the command; transmit, to the host device, a response to acknowledge the power down command; and enter, after the response is transmitted a low power mode state or an off state for one or more resources associated with the memory device.
In the analogous art of power management, VILLA teaches receiving, from a host device, a command to disable a background operation associated with the memory device (Fig. 4 illustrates host issuing a command 404 (i.e. memory device receiving a command), to safely suspend (i.e. disable) the background operation 414); disabling the background operation based at least in part on the command (suspending (i.e. disabling) the background operation 414); transmitting, to the host device, a response to acknowledge the power down command (host receiving (i.e. memory device transmitting) a memory acknowledgement 412 (i.e. response)); enter, after the response is transmitted, a low power mode state or an off state for one or more resources associated with the memory device (removal of power for the memory device 418 based on the memory acknowledgement 412 (i.e. response), causing the memory device and resources within it to enter an off state),
an amount of time for the timeout associated with the background operation that is currently ongoing ([0022] teaches if the memory device is performing an operation, then the status register unit can be accessed to determine when the operation has been completed or suspended. The method includes receiving a memory acknowledgement at the host controller from the memory device in response to the controlled power off command or waiting a certain time period prior to safely suspending the background operation (i.e. timeout for the background operation) or completing the background operation at block 412 (i.e. waiting a duration of time before the ongoing background operation is timed out)).
Accordingly, it would have been obvious to a person having ordinary skill in the art having the teachings of GE and VILLA before him before the effective filing date of the invention, to incorporate VILLA’s disablement of background operations and entering an off state based on a response, with GE’s memory device performing detecting a state of maintenance operations before a hibernate command in order to enhance memory reliability and data integrity (VILLA [0010]).
However, the combination of GE and VILLA do not explicitly disclose wherein an amount of time for the timeout associated with the background operation is based on a specific type of background operation.
In the analogous art of power management, KIM teaches wherein an amount of time for the timeout associated with the background operation is based on a specific type of background operation ([0068] teaches in response to receiving the standby indication of 310, the memory system 110-b may determine a duration to delay entry into the standby mode (i.e. amount of time for the timeout), which may be a duration associated with performing at least a subset of the background operations determined at 305 (e.g., all of the operations determined at 305, fewer than all of the background operations determined at 305) (i.e. the amount of time for the timeout is associated with the background operations). In some cases, the duration may be determined at 315 based on a type of the background operations determined at 305. For example, the memory system 110-b may determine the duration at 315 based on which of the background operations determined at 305 are to be performed (e.g., relatively high-priority media management operations), or a status of the memory system 110-b (e.g., a maintenance status, a health status), such that the memory system 110-b may use characteristics (e.g., level of importance, priority) of the background operations, among other evaluations to determine the duration (i.e. the amount of time for the timeout is based on the type of background operation)).
Accordingly, it would have been obvious to a person having ordinary skill in the art having the teachings of GE, VILLA, and KIM before him before the effective filing date of the invention, to incorporate KIM’s duration of delayed entry into standby based on the type of background operation, with GE and VILLA’s memory device in order to support an improved balance between reduced power consumption and management of memory system maintenance (KIM [0011]).
However, while VILLA teaches disabling the background operation and transmitting a response to the host, the combination of GE, VILLA, and KIM do not explicitly disclose disabling the background operation prior to transmitting a response to the host device,
In the analogous art of low power mode management, BALDWIN also teaches disabling the background operation and response, but further teaches disabling the background operation prior to transmitting a response to the host device ([0040] disable the background processes (i.e. background operations) prior to notifying (i.e. transmitting the response)).
Accordingly, it would have been obvious to a person having ordinary skill in the art having the teachings of GE, VILLA, KIM, and BALDWIN before him before the effective filing date of the invention, to incorporate BALDWIN’s order of disabling the background operation and response with GE, VILLA, and KIM’s memory device disabling background operations before entering a low power state to preserve power when device is in a low power state (BALDWIN [0013]).
Regarding Claim 9, GE, VILLA, KIM and BALDWIN disclose the memory device of claim 8. VILLA further teaches receiving the command based at least in part on a background operation status associated with the memory device (Fig. 4 illustrates host issuing a command 404 (i.e. memory device receiving a command), based on checking if the memory device is performing an operation 408 (i.e. background operation status).
Regarding Claim 10, GE, VILLA, KIM and BALDWIN disclose the memory device of claim 8. GE further discloses wherein the power down command is to cause the memory device to enter into one of: a power down mode, a sleep mode, or a deep sleep mode ([0010] teaches a hibernate command is to cause the memory device to enter the low power mode (i.e. power down mode).
Regarding Claim 12, GE, VILLA, KIM and BALDWIN disclose the memory device of claim 8. BALDWIN further teaches disabling the background operation prior to the response being transmitted to protect against overcurrent at the memory device ([0040] teaches disabling background processes (i.e. background operations) prior to notifying (i.e. transmitting a response) which would prevent background processes from continuing to operate after notifying a response to the command to disable background processes, and avoid overconsuming power in the memory device).
Regarding Claim 13, GE, VILLA, KIM and BALDWIN disclose the memory device of claim 8. GE further discloses wherein the memory device is a non-volatile memory device (Fig. 2 illustrates non-volatile memory 210).
Claims 11 and 14 are rejected under 35 U.S.C 103 as being unpatentable over GE, in view of VILLA, in view of KIM, in view of BALDWIN, and further in view of SHIN.
Regarding Claim 11, GE, VILLA, KIM and BALDWIN disclose the memory device of claim 8.
However, the combination of GE, VILLA, KIM, and BALDWIN do not explicitly disclose wherein the one or more resources includes one or more power rails or one or more clocks associated with the memory device.
In analogous art of power management, SHIN teaches wherein the one or more resources includes one or more power rails or one or more clocks associated with the memory device (Fig. 1 illustrates power rails VCC 132a, VCCQ2 132b, and VCCQ 132c associated with the memory device 130).
Accordingly, it would have been obvious to a person having ordinary skill in the art having the teachings of GE, VILLA, KIM, BALDWIN, and SHIN before him before the effective filing date of the invention, to incorporate GE, VILLA, KIM, and BALDWIN’s memory device transitioning to low power states with SHIN’s power rails in a UFS device to reduce power consumption in low power modes (SHIN [0008]).
Regarding Claim 14, GE, VILLA, KIM and BALDWIN disclose the memory device of claim 8.
However, the combination of GE, VILLA, KIM, and BALDWIN do not explicitly disclose wherein the host device is a universal flash storage (UFS) host and the memory device is a UFS device.
In analogous art of power management, SHIN teaches wherein the host device is a universal flash storage (UFS) host and the memory device is a UFS device (Fig. 1 illustrates a host device 110 and a flash memory device 130).
Accordingly, it would have been obvious to a person having ordinary skill in the art having the teachings of GE, VILLA, KIM, BALDWIN, and SHIN before him before the effective filing date of the invention, to incorporate GE, VILLA, KIM, and BALDWIN’s memory device transitioning to low power states with SHIN’s UFS host and UFS memory device as UFS is well-suited for applications where high-performance demands are seen in conjunction with low power consumption requirements (SHIN [0003]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/L.A./Examiner, Art Unit 2175
/Paul Yen/Primary Examiner, Art Unit 2175
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