DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yamashita et al, (Yamashita, US 2024/0038815 A1).
Regarding claim 1, Yamashita shows a pixel comprising: a first sub-pixel (23R and 23L in FIG. 38) comprising a plurality of first photodiodes (photoelectric 23L/23R) and a first reset transistor (TR1); and a second sub-pixel (23R and 23L in FIG. 38) comprising a plurality of second photodiodes (photoelectric 23L/23R) and a second reset transistor (TR2), wherein the first sub-pixel shares a floating diffusion node ( wiring 73 in FGI. 38 and [0475-0480]) with the second sub-pixel, and wherein a length in a first direction of a metal line for sharing the floating diffusion node is shorter ( see the connection to TR1 and TR2) than a length in the first direction of a line connecting a center point of the first sub-pixel to a center point of the second sub-pixel ( see the connection of wire in X direction in FIG. 38).
Regarding claim 2, Yamashita shows a pixel comprising, wherein a first floating diffusion region (FD1) included in the first sub-pixel (23R/23L) is electrically connected to a second floating diffusion region (FD2) included in the second sub-pixel by the metal line (metal line 73).
Regarding claim 3, Yamashita shows a pixel comprising, wherein the first floating diffusion region (FD1/FD2) is between a photoelectric conversion region corresponding to a first photodiode (23R) adjacent to the second sub-pixel from among the plurality of first photodiodes (23L) and the first reset transistor (TR1), and wherein the second floating diffusion region is between a photoelectric conversion region corresponding to a second photodiode adjacent to the first sub-pixel from among the plurality of second photodiodes and the second reset transistor (TR2).
Regarding claim 4, Yamashita shows a pixel comprising, wherein a structure of the first floating diffusion (FD1) region is symmetrical to a structure of the second floating diffusion region (FD2).
Regarding claim 5, Yamashita shows a pixel comprising, wherein the first floating diffusion region (FD1) and the second floating diffusion region (FD2) are in an L-shape in a view from above the pixel (see FIG. 38).
Regarding claim 6, Yamashita shows a pixel comprising, wherein the first floating diffusion region (FD1) is in a direction adjacent to the second sub-pixel within the first sub-pixel (23L/23R), and wherein the second floating diffusion region is in a direction adjacent to the first sub-pixel within the second sub-pixel (23R/23L).
Regarding claim 7, Yamashita shows a pixel comprising, wherein the first sub-pixel comprises four first photodiodes (PD1), and wherein the second sub-pixel comprises four second photodiodes (PD2).
Regarding claim 8, Yamashita shows a pixel comprising a first sub-pixel (23L/23r); and a second sub-pixel (23L/23r), wherein the first sub-pixel comprises: a first plurality of photoelectric conversion regions (PD1) comprising a first photoelectric conversion region (PD1), a second photoelectric conversion region, a third photoelectric conversion region (PD2), and a fourth photoelectric conversion region; and a first floating diffusion region (FD1), wherein the first plurality of photoelectric conversion regions and the first floating diffusion region are spaced apart in a direction perpendicular to the first plurality of photoelectric conversion regions (see FIG. 38), wherein the second sub-pixel comprises: a second plurality of photoelectric conversion regions comprising a fifth photoelectric conversion region, a sixth photoelectric conversion region, a seventh photoelectric conversion region, and an eighth photoelectric conversion region; and a second floating diffusion region, wherein the second plurality of photoelectric conversion regions and the second floating diffusion region are spaced apart in a direction perpendicular to the second plurality of photoelectric conversion regions (see FIG. 38 i.e. there are plurality of PDs) , wherein the first floating diffusion region is connected to the second floating diffusion region by a first metal line, wherein the first floating diffusion region is above the first plurality of photoelectric conversion regions, and wherein the second floating diffusion region is above the second plurality of photoelectric conversion regions (see FIG. 38).
Regarding claim 9, Yamashita shows a pixel comprising, wherein the first floating diffusion region (FD1) and the second floating diffusion region (FD2) are in an L-shape in a view from above the pixel (see FIG. 38).
Regarding claim 10, Yamashita shows a pixel comprising, wherein the first floating diffusion region (FD1) is adjacent to a first reset transistor included in the first sub-pixel, and the second floating diffusion region (FD2) is adjacent to a second reset transistor (TR2) included in the second sub-pixel.
Regarding claim 11, Yamashita shows a pixel comprising, wherein a location of the first reset transistor (TR1) is symmetrical to a location of the second reset transistor (TR2).
Regarding claim 12, Yamashita shows a pixel comprising, wherein a location of a first source follower transistor (TR1) included in the first sub-pixel is symmetrical to a location of a second source follower transistor included in the second sub-pixel (23R/23L).
Regarding claim 13, Yamashita shows a pixel comprising, wherein the first source follower transistor is connected to the second source follower transistor by a second metal line (see FIG. 19 with respect to FIG. 38).
Regarding claim 14, Yamashita shows a pixel comprising, wherein a length of the first metal line is equal to a length of the second metal line (see Fig. 38).
Regarding claim 15, Yamashita shows a pixel comprising, wherein the length of the first metal line and the length of the second metal line are shorter than a length of a line connecting a center point of the first sub-pixel to a center point of the second sub-pixel in a first direction (see FIG. 38).
Regarding claim 16, Yamashita shows a pixel having a 2 x 4 structure (see FIG. 38), the pixel comprising: a first sub-pixel (23R/23L); and a second sub-pixel (23R/23L), wherein a structure of the first sub-pixel is symmetrical to a structure of the second sub-pixel with respect to a center point of the pixel (see FIG. 38), and wherein a length of a first metal line connecting a first floating diffusion region of the first sub-pixel to a second floating diffusion region included in the second sub-pixel is shorter than a length of a line connecting a center point of the first sub-pixel to a center point of the second sub-pixel (see FIG. 38).
Regarding claim 17, Yamashita shows a pixel comprising, wherein the first floating diffusion region (FD1) is in a direction biased to a first diagonal direction with respect to the center point of the first sub-pixel (23R), wherein the second floating diffusion region (FD2) is in a direction biased to a second diagonal direction with respect to the center point of the second sub-pixel, and wherein the first diagonal direction is perpendicular to the second diagonal direction (see FIG. 38).
Regarding claim 18, Yamashita shows a pixel comprising, wherein the first floating diffusion region and the second floating diffusion region are in an L-shape in a view from above the pixel (see FIG. 38).
Regarding claim 19, Yamashita shows a pixel comprising, wherein the first floating diffusion region is adjacent to a reset transistor included in the first sub-pixel, and wherein the second floating diffusion region is adjacent to a reset transistor included in the second sub-pixel (see FIG.38).
Regarding claim 20, Yamashita shows a pixel comprising, wherein a location of a source follower transistor included in the first sub-pixel is symmetrical to a location of a source follower transistor included in the second sub-pixel (see FIG. 38).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893
