CTNF 18/896,267 CTNF 98332 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. The information disclosure statements (IDS) submitted on 09/25/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The independent claims 1 , 8 and 17 recite “ receiving an error message …; generating a language-based machine learning (ML) prompt …; and determining an adjustment to the system design ...” as drafted cover an abstract idea of data analysis/retrieval and mental steps. More specifically, the “receiving an error message associated with a system design of a field-programmable gate array (FPGA); generating a language-based machine learning (ML) prompt based at least on the error message; and determining an adjustment to the system design based on providing the language-based ML prompt to one or more language-based ML models trained on error messages of prior system designs” which requires just data analysis / retrieval step and mental process. For instance, an electronic engineer specialized in designing chips like FPGA can collect/receive an error message associated with a system design of a field-programmable gate array (FPGA), put those error messages in a spreadsheet, generate necessary queries/prompts based on the error messages, and determine necessary corrective changes/adjustment to the system design based on error messages of prior system designs data collected with the spreadsheet. The claimed invention is, therefore, directed to an abstract idea and a mental process without significantly more and thus, claims 1, 8 and 17 are rejected under 35 U.S.C. 101. Similarly, the dependent claims 2-7 , 9-16 and 18-20 recite similar claim language as in claims 1, 8 and 17. Claims 2 recites “identifying one or more subsystems of the compiler software associated with the error message, wherein the language-based machine learning (ML) prompt indicates the one or more subsystems,” which requires just a mental step of identifying one or more subsystems associated with the error message. Thus, these claim 2 is directed to an abstract idea. Claim 3 recites “applying the adjustment to the system design of the FPGA to generate an adjusted system design; receiving a compilation result of the adjusted system design; and providing the adjustment and the compilation result to the one or more language-based ML models as training data,” which also requires just a mental step and data collection and retrieval. An engineer who is an expert in FPGA design can mentally apply the change/adjustment to the system design of the FPGA to produce/generate an adjusted system design, receive a compilation of the adjusted system design on a paper or spreadsheet, and provide the adjustment and the compilation result. Thus, claims 3 is directed to an abstract idea. Claim 4 recites “one or more language-based ML models are trained on identified solutions to the error messages of the prior system designs,” which requires just a simple procedure of training based on error messages of the prior system designs that can be easily performed by a human. Thus, claim 4 is directed to an abstract idea. Claim 5 recites “one or more language-based ML models produce a script output,” which requires just a mental step of producing a script output which any human can do mentally and using pen and paper. Thus, claim 5 is directed to an abstract idea. Claim 6 recites “implementing the adjustment to the system design according to the script to generate an adjusted system design,” which requires just a simple mental step that can be easily performed by a human mind, for example by the specialized FPGA engineer, by taking a look at the script/text written related to the issues or errors in the FPGA design. Thus, claim 6 is directed to an abstract idea. Claim 7 recites “compiling the adjusted system design,” which requires just a simple data retrieval and archival procedure and a metal step that can be easily performed mentally by collecting and compiling the changes made in a system design. Thus, claim 7 is directed to an abstract idea. Claim 9 recites “one or more language-based ML models comprise a large language model (LLM),” which is basically consisting of additional elements as described below. Thus, claim 9 is directed to an abstract idea. Claim 10 recites “one or more language-based ML models are local to the data processing system,” which simply introduces additional elements that perform locally. Thus, claims 10 is directed to an abstract idea. Claim 11 recites “one or more language-based ML models are remote to the data processing system,” which simply introduces additional elements that perform remotely. Claim 12 recites “the code portion indicated in the error message; and a natural language prompt indicating one or more aspects of the system design,” which is a mental step that just require a code indicating the error message, and a prompt or query indicating one or more aspects of the system design. Thus, claim 12 is directed to an abstract idea. Claim 13 recites “the natural language prompt specifies an indication of a desired output of the one or more language-based ML models,” which just involves additional elements as described below. Thus, claim 13 is directed to an abstract idea. Claim 14 recites “the one or more language-based ML models provide an output in response to the language-based ML prompt as a script,” which just require a metal step of producing an output based on a script prompt. Thus, claim 14 is directed to an abstract idea. Claim 15 recites “the script is readable by the data processing system and, when executed by the data processing system, causes the data processing system to adjust the system design,” which require just a mental step and data retrieval with script, and that can be performed with a human brain to adjust/change a system design. Thus, claim 15 directed to an abstract idea. Claim 16 recites “the FPGA, the FPGA communicatively coupled to the data processing system,” which just requires a mental step by, for example, an expert in chip/FPGA to communicatively couple to a data processing system that can be implemented using a generalized computer. Thus, claim 16 is directed to an abstract idea. Claim 18 recites “the error message comprises a compilation error message generated in response to a compilation attempt of the system design,” which requires just a mental step and compiling with a spreadsheet, for instance, of error messages which are produced as a result of the attempts of compiling system design. Thus, claim 18 is directed to an abstract idea. Claim 19 recites “one or more language-based ML models are trained on identified solutions to the error messages of the prior system designs,” which just requires a mental step of using just one or more models which make use of identified solutions to the error messages of the prior system designs, and also this claim involves additional elements, as described below. Thus, claim 19 is directed to an abstract idea. Claim 20 recites “the language-based ML prompt comprises an indication of one or more parameters or subsystems of the system design,” which requires just a mental step making use of additional elements. The claimed prompt here can be a mentally introduced query. Thus, claim 20 is directed to an abstract idea. Thus, claims 1-20 as drafted cover a mental process and abstract idea of data gathering/retrieval and analysis/processing steps, and they are mental processes directed to an abstract idea of implementing mathematical formulae for data processing and data analysis using a conventional/generic (general-purpose) computer as well and thus, all the claims are directed to an abstract idea. This judicial exception is not integrated into a practical application. In particular, claims 1-5, 8-14, 17 and 19-20 recite additional element of “language-based machine learning (ML) prompt” and “language-based machine learning (ML) model” as per the independent and dependent claims; claim 17 recites an additional element of “processor” as per an independent claim (Cakir, para 0012 implementation of designing … using a system-on-chip (SoC), including a general-purpose processor); claims 8, 10-11 and 15-16 recite an additional element of “data processing system” as per independent and dependent claims (Comin, para 0002, The invention is furthermore concerned with a corresponding data processing apparatus …; [“data processing apparatus” as “data processing system”]); and claim 2 recites an additional element of “compiler software” as per an independent claim. Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea. Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. There is no indication that the combination of elements improves the functioning of a computer or improves any other technology. Their collective functions merely provide conventional general purpose computer implementation. Claims 1-20, are therefore not drawn to patent eligible subject matter as they are directed to an abstract idea without significantly more. Thus, the claimed invention is directed to an abstract idea and a mental process without significantly more and thus, claims 1-20 are rejected under 35 U.S.C. 101. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to the integration of the abstract idea into a practical application, the additional element of using a computer is noted as a general computer as noted. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Further, the additional limitation in the claims noted above are directed towards insignificant solution activity. The claims are not patent eligible. Dependent claims 2-7, 9-16 and 18-20 are also directed toward an abstract idea and do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea. Therefore, claims 1-20 do not contain patent eligible subject matter that has been identified by the courts. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-4, 6-8 and 12-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cakir et al. Pat App No. US 20240086445 A1 (Cakir) . Regarding Claim 1, Cakir discloses a method, comprising: receiving an error message associated with a system design of a field-programmable gate array (FPGA) (Cakir, para 0064, the predictive application 708 receives an IC troubleshooting query from the user. In case the user is operating the emulation platform 704 , the IC troubleshooting query is input as an emulation issue to the predictive application 708 . In case the user encounters the issue while evaluating the test chip 706 , the IC troubleshooting query is input as a chip issue to the predictive application 708 . The predictive application processes the IC troubleshooting query and retrieves resolution data from an expert system library 710 ); generating a language-based machine learning (ML) prompt based at least on the error message (Cakir, para 0062, the predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various RTL designs and generates recommendations to remediate the error or failure; Cakir, para 0030, the predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various register transfer level (RTL) designs and generates recommendations to remediate the error or failure. The recommendations may include a number of prior related tickets that are relevant to the IC troubleshooting query (to assist with self-debugging), an expert technician assigned to the IC troubleshooting query, as well as a self-help guide with step-by-step instructions for solving the issue. The predictive application may be referred to as a TroubleSnap Dr. Machine Learning and Natural Language Processing (NLP)-based System for SoC Troubleshooting; [i.e., “query” as “prompt”]); and determining an adjustment to the system design based on providing the language-based ML prompt to one or more language-based ML models trained on error messages of prior system designs (Cakir, para 0062-0064, The predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various RTL designs and generates recommendations to remediate the error or failure. The SoC expert libraries may be stored in company databases… FIG. 7 is a block diagram illustrating applicability of a machine learning natural language processing-based SoC troubleshooting application, in accordance with aspects of the present disclosure. A baseline SoC 702 may include numerous components, such as those illustrated generically in FIG. 1 or the components illustrated more specifically in FIG. 7 . An emulation platform 704 may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of an RTL design of the SoC 702 . A test chip 706 (e.g., application specific integrated chip (ASIC)) may also enable testing of the RTL design of the SoC 702 . The test chip 706 enables later stage testing to locate and fix issues of the design … the IC troubleshooting query is input as a chip issue to the predictive application 708 . The predictive application processes the IC troubleshooting query and retrieves resolution data from an expert system library 710 . Based on the retrieved results, the predictive application 708 outputs a recommendation; Cakir, para 0030, The predictive application may be referred to as a TroubleSnap Dr. Machine Learning and Natural Language Processing (NLP)-based System for SoC Troubleshooting; [i.e., “query input to the predictive application” as “prompt input to the language-based ML”; “The SoC expert libraries may be stored in company databases” as “error messages of prior system designs”]; Cakir, para 0074, A trained model 916 receives the topic clusters 914 and communicates with a recommender engine 918 (also referred to as the recommender system 818 in FIG. 8 ). The recommender engine 918 outputs a category, relevant tickets, and an assigned technician. The agent application 902 searches an emulation failures look up table (LUT) 920 (also referred to as the expert generated resolution LUT 812 in FIG. 8 ) to map the issue to relevant corrective steps associated with another user with a similar or identical setup. In other words, the agent application 902 recognizes the issue and generates relevant corrective steps in order to troubleshoot the problem. For example, a user self-help guide may be considered a failure fix remedy 922; Cakir, para 0030, The troubleshooting system of the present disclosure improves the user experience with a recommendation engine that generates similar issues and potential remedies for the user's trouble ticket… The recommendations may include a number of prior related tickets that are relevant to the IC troubleshooting query; Cakir, para 0068, A trained model 808 , machine learning (ML) annotated database 810 , and an expert generated resolution look-up table (LUT) 812 are created based on the clustered tickets. The trained model 808 is used for inference and may be trained against a full comment body of previous resolution efforts; [“trained models… based on the clustered tickets… trained against a full comment body of previous resolution efforts… recommendations may include a number of prior related tickets that are relevant to the IC troubleshooting query” as “prompt to one or more language-based ML models trained on error messages of prior system designs”; “query” as “prompt”]). Regarding Claim 2, Cakir discloses the method of claim 1, wherein the error message is generated based on compiler software, and comprising: identifying one or more subsystems of the compiler software associated with the error message, wherein the language-based machine learning (ML) prompt indicates the one or more subsystems (Cakir, 0025 – 0033, Several aspects of troubleshooting systems will now be presented with reference to various apparatuses and techniques…These elements may be implemented using hardware, software, or combinations thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. As system-on-chips (SoCs) become more complex, the number of problems found in those SoCs may increase. Resources, such as technicians and debuggers, for addressing the problems (e.g., trouble tickets) may be limited due to a high volume of trouble tickets, limited time for solving the issues, and an increased complexity of the issues. Moreover, the know-how for debugging can be local. Consequently, it may be desirable to use a data driven approach that learns patterns from big data to address and debug the issues related to SoCs. SoCs may be tested with emulation platforms and test chips. Emulation platforms, for example, may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of chip designs. After a design has been approved, test chips (e.g., application specific integrated chips (ASICs)) may be fabricated. Test chips enable testing of the silicon to locate and fix issues before committing to large scale production of the chip. Aspects of the present disclosure introduce a machine learning and natural language processing-based integrated circuit (IC) troubleshooting system, such as an SoC troubleshooting system… The troubleshooting system of the present disclosure improves the user experience with a recommendation engine that generates similar issues and potential remedies for the user's trouble ticket. More specifically, the predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various register transfer level (RTL) designs and generates recommendations to remediate the error or failure. The recommendations may include a number of prior related tickets that are relevant to the IC troubleshooting query (to assist with self-debugging), an expert technician assigned to the IC troubleshooting query, as well as a self-help guide with step-by-step instructions for solving the issue. The predictive application may be referred to as a TroubleSnap Dr. Machine Learning and Natural Language Processing (NLP)-based System for SoC Troubleshooting. FIG. 1 illustrates an example implementation of a system-on-chip (SoC) 100 , which may include a central processing unit (CPU) 102 or a multi-core CPU… The SoC 100 may also include additional processing blocks tailored to specific functions, such as a GPU 104 , a DSP 106 , a connectivity block 110 , which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, and the like, and a multimedia processor 112 that may, for example, detect and recognize gestures. In one implementation, the NPU is implemented in the CPU, DSP, and/or GPU. The SoC 100 may also include a sensor processor 114 , image signal processors (ISPs) 116 , and/or navigation module 120 , which may include a global positioning system. The SoC 100 may be based on an ARM instruction set. In an aspect of the present disclosure, the instructions loaded into the general-purpose processor 102 may comprise code to receive an integrated circuit (IC) troubleshooting query for an IC; [i.e., “troubleshooting systems … implemented using hardware, software, or combinations thereof... implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system… SoCs [i.e., system-on-chips (SoCs)] may be tested with emulation platforms and test chips. Emulation platforms, for example, may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of chip designs… Aspects of the present disclosure introduce a machine learning and natural language processing-based integrated circuit (IC) troubleshooting system” as “identifying one or more subsystems of the compiler software associated with the error message, wherein the language-based machine learning (ML) prompt indicates the one or more subsystems”; “FIG. 1 illustrates an example implementation of a system-on-chip (SoC) 100 , which may include a central processing unit (CPU) 102 or a multi-core CPU… The SoC 100 may also include additional processing blocks tailored to specific functions, such as a GPU 104 , a DSP 106 , a connectivity block 110 , ... The SoC 100 may be based on an ARM instruction set… the instructions loaded into the general-purpose processor 102 may comprise code to receive an integrated circuit (IC) troubleshooting query for an IC” as “… prompt [i.e., IC troubleshooting query] indicates the one or more subsystems [i.e., the SoC system and the subsystems like the CPU, GPU, … in Figure 1 of Cakir]”]). Regarding Claim 3, Cakir discloses the method of claim 1, comprising: applying the adjustment to the system design of the FPGA to generate an adjusted system design (Cakir, para 0027, SoCs may be tested with emulation platforms and test chips. Emulation platforms, for example, may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of chip designs. After a design has been approved, test chips (e.g., application specific integrated chips (ASICs)) may be fabricated. Test chips enable testing of the silicon to locate and fix issues); receiving a compilation result of the adjusted system design (Cakir, para 0059 - 0060, The troubleshooting system employs an SoC domain-aware automated design troubleshooting methodology. By employing specialized natural language processing (NLP) in the Emulation and RMA troubleshooting process, the troubleshooting system is able to include the chip's designer as well as the chip's debugger in the feedback loop… The troubleshooting system of the present disclosure improves the user experience with a recommendation engine that generates similar issues and potential remedies for the user's trouble ticket. In some implementations, the results are obtained in under four milliseconds); and providing the adjustment and the compilation result to the one or more language-based ML models as training data (Cakir, para 0067, FIG. 8 is a block diagram illustrating training and inference by the machine learning natural language processing-based SoC troubleshooting application). Regarding Claim 4, Cakir discloses the method of claim 1, wherein the one or more language-based ML models are trained on identified solutions to the error messages of the prior system designs (Cakir, para 0070-0071, A recommender system 818 receives the user input 816 and then applies user customizable filters. For example, the input may be filtered by whether the test chip (e.g., ASIC) or the emulator had encountered the issue triggering the trouble ticket. Other filters, such as sub-block, subsystem, etc., may also be employed. The recommender system 818 uses the trained model 808 and the annotated database 810 to generate output. The output may include a category for the IC troubleshooting query, a number of top relevant tickets 820 that are relevant to the IC troubleshooting query, and an expert technician assigned to the IC troubleshooting query. The expert technician may be selected as the person with the most expertise to help with solving the issues raised by the IC troubleshooting query. The recommender system 818 may recommend the expert technician based on the determined category. The category determined by the recommender system 818 may be used to perform a look up at the expert generated resolution look up table 812 in order to find well-defined solutions). Regarding Claim 6, Cakir discloses the method of claim 5, implementing the adjustment to the system design according to the script to generate an adjusted system design (Cakir, para 0064, The predictive application processes the IC troubleshooting query and retrieves resolution data from an expert system library 710 . Based on the retrieved results, the predictive application 708 outputs a recommendation. In case the user is a business to business (B2B) emulation farm customer 712 , the output includes similar issues and a remedy or fix recommendation. After the issues with the emulation platform have been solved, a test chip may be fabricated; para 0086-0088, FIG. 14 is a flow diagram illustrating an example process 1400… the process 1400 may include receiving an integrated circuit (IC) troubleshooting query for an IC. The IC troubleshooting query is received from a user (block 1402 ). For example, the IC troubleshooting query may be associated with an emulation platform for the IC or a test chip implementation for the IC… the process 1400 may also include generating a recommendation in response to the IC troubleshooting query, based on the resolution data (block 1408 ). For example, the recommendation may comprise relevant historical resolution data and an expert technician assigned to the troubleshooting query; [i.e., “Based on the retrieved results, i.e. results from the predictive application processing the IC troubleshooting query, the predictive application 708 outputs a recommendation... output includes …issues and a remedy or fix recommendation. After the issues with the emulation platform have been solved, a test chip may be fabricated” as “implementing the adjustment to the system design”; “generating a recommendation in response to the IC troubleshooting query, based on the resolution data…” as “according to the script to generate an adjusted system design”]). Regarding Claim 7, Cakir discloses the method of claim 6, comprising compiling the adjusted system design (Cakir, para 0057-0059, SoCs [i.e., system-on-chips] may be tested with emulation platforms and test chips. Emulation platforms, for example, may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of chip designs. After a design has been approved, test chips (e.g., application specific integrated chips (ASICs)) may be fabricated. Test chips enable testing of the silicon to locate and fix issues before committing to large scale production of the chip… the present disclosure introduce a machine learning and natural language processing-based SoC troubleshooting system… the machine learning and natural language processing-based troubleshooting system continuously updates a machine derived mapping between experience and a query-able knowledge base; [i.e., “the machine learning and natural language processing-based troubleshooting system continuously updates a machine derived mapping between experience and a query-able knowledge base” as “compiling the adjusted system design”]). Regarding Claim 8, Cakir discloses a system, comprising: one or more language-based machine learning (ML) models trained on error messages of prior system designs (Cakir, para 0029-0030, The troubleshooting system employs an SoC domain-aware automated design troubleshooting methodology…A comment agnostic assignment system may be employed for new issues. Aspects provide a predictive system focusing on root causes, learning from prior resolutions to identify an optimal resolution or to troubleshoot errors. Dynamic parsing may occur in the data preparation and tokenization processes for SoC-specific combinations. The troubleshooting system of the present disclosure improves the user experience with a recommendation engine that generates similar issues and potential remedies for the user's trouble ticket. More specifically, the predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various register transfer level (RTL) designs and generates recommendations to remediate the error or failure. The recommendations may include a number of prior related tickets that are relevant to the IC troubleshooting query (to assist with self-debugging), an expert technician assigned to the IC troubleshooting query, as well as a self-help guide with step-by-step instructions for solving the issue; Cakir, para 0030, The troubleshooting system of the present disclosure improves the user experience with a recommendation engine that generates similar issues and potential remedies for the user's trouble ticket… The recommendations may include a number of prior related tickets that are relevant to the IC troubleshooting query; Cakir, para 0068, A trained model 808 , machine learning (ML) annotated database 810 , and an expert generated resolution look-up table (LUT) 812 are created based on the clustered tickets. The trained model 808 is used for inference and may be trained against a full comment body of previous resolution efforts; [i.e., “troubleshooting system … improves … recommendation engine that generates similar issues and potential remedies for the user's trouble ticket… The recommendations may include a number of prior related tickets…The trained model … may be trained against a full comment body of previous resolution efforts” as “language-based machine learning (ML) models trained on error messages of prior system designs”]); and a data processing system (Cakir, para 0026-0031, it may be desirable to use a data driven approach that learns patterns from big data to address and debug the issues related to SoCs… FIG. 1 illustrates an example implementation of a system-on-chip (SoC) 100 , which may include a central processing unit (CPU) 102 or a multi-core CPU… a graphics processing unit (GPU) 104 , in a memory block associated with a digital signal processor (DSP); [i.e., Figure 1 of Cakir is a “data processing system” that includes CPU, GPU, …, Memory, DSP, …] ) comprising: an error response component to run on the data processing system (Cakir, para 0027, SoCs may be tested with emulation platforms and test chips. Emulation platforms, for example, may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of chip designs. After a design has been approved, test chips (e.g., application specific integrated chips (ASICs)) may be fabricated. Test chips enable testing of the silicon to locate and fix issues before committing to large scale production of the chip) to: receive an error message associated with a system design of a field-programmable gate array (FPGA) (Cakir, para 0064, the predictive application 708 receives an IC troubleshooting query from the user. In case the user is operating the emulation platform 704 , the IC troubleshooting query is input as an emulation issue to the predictive application 708 . In case the user encounters the issue while evaluating the test chip 706 , the IC troubleshooting query is input as a chip issue to the predictive application 708 . The predictive application processes the IC troubleshooting query and retrieves resolution data from an expert system library 710 ); and generate a language-based machine learning (ML) prompt for the one or more language-based machine learning (ML) models based at least on the error message (Cakir, para 0062, the predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various RTL designs and generates recommendations to remediate the error or failure; Cakir, para 0030, the predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various register transfer level (RTL) designs and generates recommendations to remediate the error or failure. The recommendations may include a number of prior related tickets that are relevant to the IC troubleshooting query (to assist with self-debugging), an expert technician assigned to the IC troubleshooting query, as well as a self-help guide with step-by-step instructions for solving the issue. The predictive application may be referred to as a TroubleSnap Dr. Machine Learning and Natural Language Processing (NLP)-based System for SoC Troubleshooting; [i.e., “query” as “prompt”]). Regarding Claim 12, Cakir discloses the system of claim 8, wherein the error message indicates a code portion, and wherein the language-based machine learning (ML) prompt comprises: the code portion indicated in the error message (para 0033, The instructions loaded into the general-purpose processor 102 may also comprise code to generate a recommendation in response to the IC troubleshooting query, based on the resolution data. The instructions loaded into the general-purpose processor 102 may comprise code to output the recommendation to the user); and a natural language prompt indicating one or more aspects of the system design (para 0063, FIG. 7 is a block diagram illustrating applicability of a machine learning natural language processing-based SoC troubleshooting application… A test chip 706 (e.g., application specific integrated chip (ASIC)) may also enable testing of the RTL design of the SoC 702 . The test chip 706 enables later stage testing to locate and fix issues of the design). Regarding Claim 13, Cakir discloses the system of claim 12, wherein the natural language prompt specifies an indication of a desired output of the one or more language-based ML models (para 0029, the machine learning and natural language processing-based troubleshooting system continuously updates a machine derived mapping between experience and a query-able knowledge base. The troubleshooting system employs an SoC domain-aware automated design troubleshooting methodology). Regarding Claim 14, Cakir discloses the system of claim 8, wherein the one or more language-based ML models provide an output in response to the language-based ML prompt as a script (Cakir, para 0027, SoCs may be tested with emulation platforms and test chips. Emulation platforms, for example, may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of chip designs. After a design has been approved, test chips (e.g., application specific integrated chips (ASICs)) may be fabricated. Test chips enable testing of the silicon to locate and fix issues before committing to large scale production of the chip. Aspects of the present disclosure introduce a machine learning and natural language processing-based integrated circuit (IC) troubleshooting system, such as an SoC troubleshooting system.… The SoC 100 may be based on an ARM instruction set. In an aspect of the present disclosure, the instructions loaded into the general-purpose processor 102 may comprise code to receive an integrated circuit (IC) troubleshooting query for an IC… The instructions loaded into the general-purpose processor 102 may also comprise code to generate a recommendation in response to the IC troubleshooting query; [“machine learning and natural language processing-based integrated circuit (IC) troubleshooting system… generate a recommendation in response to the IC troubleshooting query” as “language-based ML models provide an output in response to…ML prompt”; “recommendation” as “output”]). Regarding Claim 15, Cakir discloses the system of claim 14, wherein the script is readable by the data processing system and, when executed by the data processing system, causes the data processing system to adjust the system design (Cakir, para 0026-0027, As system-on-chips (SoCs) become more complex, the number of problems found in those SoCs may increase. Resources, such as technicians and debuggers, for addressing the problems (e.g., trouble tickets) may be limited due to a high volume of trouble tickets, limited time for solving the issues, and an increased complexity of the issues. Moreover, the know-how for debugging can be local. Consequently, it may be desirable to use a data driven approach that learns patterns from big data to address and debug the issues related to SoCs… SoCs may be tested with emulation platforms and test chips. Emulation platforms, for example, may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of chip designs. After a design has been approved, test chips (e.g., application specific integrated chips (ASICs)) may be fabricated. Test chips enable testing of the silicon to locate and fix issues; Cakir, para 0063, … The test chip 706 enables later stage testing to locate and fix issues of the design; [“test chips… locate and fix issues of the design” as “adjust the system design”]). Regarding Claim 16, Cakir discloses the system of claim 8, comprising the FPGA, the FPGA communicatively coupled to the data processing system (Cakir, para 0027-0031 System-on-chips (SoCs) may be tested with emulation platforms and test chips. Emulation platforms, for example, may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of chip designs. After a design has been approved, test chips (e.g., application specific integrated chips (ASICs)) may be fabricated. Test chips enable testing of the silicon to locate and fix issues before committing to large scale production of the chip… FIG. 1 illustrates an example implementation of a system-on-chip (SoC) 100 , which may include a central processing unit (CPU) 102 or a multi-core CPU… a graphics processing unit (GPU) 104 , in a memory block associated with a digital signal processor (DSP); [i.e., Figure 1 of Cakir involves an implementation of field programmable gate arrays (FPGAs) or SoCs and this “data processing system” includes CPU, GPU, …, Memory, DSP unit, …, i.e., the FPGA is communicatively coupled to the data processing system] .). Regarding Claim 17, Cakir discloses a tangible, non-transitory, and computer-readable medium, storing instructions thereon, wherein the instructions, when executed, are to cause a processor (Cakir, para 0008, a non-transitory computer-readable medium with program code recorded thereon is disclosed. The program code is executed by a processor and includes program code to receive an integrated circuit (IC) troubleshooting query for an IC, the IC troubleshooting query) to: receive an error message associated with a system design of a field-programmable gate array (FPGA) (Cakir, para 0064, the predictive application 708 receives an IC troubleshooting query from the user. In case the user is operating the emulation platform 704 , the IC troubleshooting query is input as an emulation issue to the predictive application 708 . In case the user encounters the issue while evaluating the test chip 706 , the IC troubleshooting query is input as a chip issue to the predictive application 708 . The predictive application processes the IC troubleshooting query and retrieves resolution data from an expert system library 710 ); generate a language-based machine learning (ML) prompt based at least on the error message (Cakir, para 0062, the predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various RTL designs and generates recommendations to remediate the error or failure; Cakir, para 0030, the predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various register transfer level (RTL) designs and generates recommendations to remediate the error or failure. The recommendations may include a number of prior related tickets that are relevant to the IC troubleshooting query (to assist with self-debugging), an expert technician assigned to the IC troubleshooting query, as well as a self-help guide with step-by-step instructions for solving the issue. The predictive application may be referred to as a TroubleSnap Dr. Machine Learning and Natural Language Processing (NLP)-based System for SoC Troubleshooting; [i.e., “query” as “prompt”]); and determine an adjustment to the system design based on providing the language-based ML prompt to one or more language-based ML models trained on error messages of prior system designs (Cakir, para 0062-0064, The predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various RTL designs and generates recommendations to remediate the error or failure. The SoC expert libraries may be stored in company databases…FIG. 7 is a block diagram illustrating applicability of a machine learning natural language processing-based SoC troubleshooting application, in accordance with aspects of the present disclosure. A baseline SoC 702 may include numerous components, such as those illustrated generically in FIG. 1 or the components illustrated more specifically in FIG. 7 . An emulation platform 704 may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of an RTL design of the SoC 702 . A test chip 706 (e.g., application specific integrated chip (ASIC)) may also enable testing of the RTL design of the SoC 702 . The test chip 706 enables later stage testing to locate and fix issues of the design, as implemented in silicon… the IC troubleshooting query is input as a chip issue to the predictive application 708 . The predictive application processes the IC troubleshooting query and retrieves resolution data from an expert system library 710 . Based on the retrieved results, the predictive application 708 outputs a recommendation; Cakir, para 0030, The predictive application may be referred to as a TroubleSnap Dr. Machine Learning and Natural Language Processing (NLP)-based System for SoC Troubleshooting; [i.e., “query input to the predictive application” as “prompt input to the language-based ML”]). Regarding Claim 18, Cakir discloses the tangible, non-transitory, and computer-readable medium of claim 17, wherein the error message comprises a compilation error message generated in response to a compilation attempt of the system design (Cakir, 0025 – 0028, Several aspects of troubleshooting systems will now be presented with reference to various apparatuses and techniques…These elements may be implemented using hardware, software, or combinations thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. As system-on-chips (SoCs) become more complex, the number of problems found in those SoCs may increase. Resources, such as technicians and debuggers, for addressing the problems (e.g., trouble tickets) may be limited due to a high volume of trouble tickets, limited time for solving the issues, and an increased complexity of the issues. Moreover, the know-how for debugging can be local. Consequently, it may be desirable to use a data driven approach that learns patterns from big data to address and debug the issues related to SoCs. SoCs may be tested with emulation platforms and test chips. Emulation platforms, for example, may be implemented with field programmable gate arrays (FPGAs) programmed to operate as virtual chips to enable testing of chip designs. After a design has been approved, test chips (e.g., application specific integrated chips (ASICs)) may be fabricated. Test chips enable testing of the silicon to locate and fix issues before committing to large scale production of the chip. Aspects of the present disclosure introduce a machine learning and natural language processing-based integrated circuit (IC) troubleshooting system, such as an SoC troubleshooting system). Regarding Claim 19, Cakir discloses the tangible, non-transitory, and computer-readable medium of claim 17, wherein the one or more language-based ML models are trained on identified solutions to the error messages of the prior system designs (Cakir, para 0070-0071, A recommender system 818 receives the user input 816 and then applies user customizable filters. For example, the input may be filtered by whether the test chip (e.g., ASIC) or the emulator had encountered the issue triggering the trouble ticket. Other filters, such as sub-block, subsystem, etc., may also be employed. The recommender system 818 uses the trained model 808 and the annotated database 810 to generate output. The output may include a category for the IC troubleshooting query, a number of top relevant tickets 820 that are relevant to the IC troubleshooting query, and an expert technician assigned to the IC troubleshooting query. The expert technician may be selected as the person with the most expertise to help with solving the issues raised by the IC troubleshooting query. The recommender system 818 may recommend the expert technician based on the determined category. The category determined by the recommender system 818 may be used to perform a look up at the expert generated resolution look up table 812 in order to find well-defined solutions; Cakir, para 0060-0062, Aspects provide a predictive system focusing on root causes, learning from prior resolutions to identify an optimal resolution or to troubleshoot errors. Dynamic parsing may occur in the data preparation and tokenization processes for SoC-specific combinations. The troubleshooting system of the present disclosure improves the user experience with a recommendation engine that generates similar issues and potential remedies for the user's trouble ticket. In some implementations, the results are obtained in under four milliseconds… The machine learning natural language processing-based SoC troubleshooting application facilitates the diagnosis and resolution of issues seen on SoCs). Regarding Claim 20, Cakir discloses the tangible, non-transitory, and computer-readable medium of claim 17, wherein the language-based ML prompt comprises an indication of one or more parameters or subsystems of the system design (Cakir, 0025 – 0031, Aspects of the present disclosure introduce a machine learning and natural language processing-based integrated circuit (IC) troubleshooting system, such as an SoC [i.e., system-on-chips] troubleshooting system… the machine learning and natural language processing-based troubleshooting system continuously updates a machine derived mapping between experience and a query-able knowledge base. The troubleshooting system employs an SoC domain-aware automated design troubleshooting methodology… More specifically, the predictive application retrieves problem (e.g., resolution) data from expert system libraries for each subsystem, and sub-block associated with various register transfer level (RTL) designs and generates recommendations to remediate the error or failure. The recommendations may include a number of prior related tickets that are relevant to the IC troubleshooting query (to assist with self-debugging), an expert technician assigned to the IC troubleshooting query, as well as a self-help guide with step-by-step instructions for solving the issue. The predictive application may be referred to as a TroubleSnap Dr. Machine Learning and Natural Language Processing (NLP)-based System for SoC Troubleshooting. FIG. 1 illustrates an example implementation of a system-on-chip (SoC) 100 , which may include a central processing unit (CPU) 102 or a multi-core CPU, in accordance with certain aspects of the present disclosure… Variables (e.g., neural signals and synaptic weights), system parameters associated with a computational device (e.g., neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108 , in a memory block associated with a CPU 102 , in a memory block associated with a graphics processing unit (GPU) 104 , in a memory block associated with a digital signal processor (DSP) 106 , in a memory block 118 , or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from a program memory associated with the CPU 102 or may be loaded from a memory block 118 ; [ “the IC troubleshooting query (using the Machine Learning and Natural Language Processing (NLP)-based System) is implemented as in FIG. 1 with a system-on-chip (SoC) 100 , which may include a central processing unit (CPU) 102 or a multi-core CPU, … and it may involve variables (e.g., neural signals and synaptic weights), system parameters associated with a computational device (e.g., neural network with weights),…GPU,…” as “the language-based ML prompt comprises an indication of one or more parameters or subsystems of the system design”]) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cakir in view of Maschmeyer Pat App No. US 20240311192 A1 (Maschmeyer) . Regarding Claim 5, Cakir discloses the method of claim 1. Cakir does not specifically disclose wherein the one or more language-based ML models produce a script output. However, Maschmeyer, in the same field of endeavor, discloses wherein the one or more language-based ML models produce a script output (Maschmeyer, para 0003, A large language model (LLM) is a type of machine learning (ML) model that is capable of generating text output, including natural language text output. A LLM may be provided with a prompt, which may be a natural language instruction that instructs the LLM to generate a desired output, including natural language text or other generative output in various desired formats ). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Maschmeyer in the method of Cakir because this would enable generation of prompts to large language models (LLMs) and improving accessibility to the LLM (Maschmeyer, para 0002 and 0008) . 07-21-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cakir in view of Comin Pat App No. US 20240403520 A1 (Comin) . Regarding Claim 9, Cakir discloses the system of claim 8. Cakir does not specifically disclose wherein the one or more language-based ML models comprise a large language model (LLM). However, Comin, in the same field of endeavor, discloses wherein the one or more language-based ML models comprise a large language model (LLM) (Comin, para 0042, The neural network is configured as a large language model, LLM, and trained with a plurality of template systems and template components in the related technical field). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Comin in the method of Cakir because this would enable software tools to be available to leverage the knowledge required for the engineer designing complex electronic systems, such as e.g. an FPGA, and some of these tools may use reinforcement learning for chip design (Comin, para 0005) . 07-21-aia AIA Claim 10-11 is rejected under 35 U.S.C. 103 as being unpatentable over Cakir in view of Spaner Pat App No. US 20250284492 A1 (Spaner) . Regarding Claim 10, Cakir discloses the system of claim 8 Cakir does not specifically disclose wherein the one or more language-based ML models are local to the data processing system. However, Spaner, in the same field of endeavor, discloses wherein the one or more language-based ML models are local to the data processing system (Spaner, para 0050, the computing device 26 may share the causal graphs with an on-premise (e.g., stored in the memory and executed by the processor of a local controller) machine-learning algorithm, large language model, artificial intelligence, and the like, in order to leverage the complex causal relationships locally ). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Spaner in the method of Cakir because this would enable providing improved techniques for identifying root causes within complex industrial automation systems (Spaner, para 0003). Regarding Claim 11, Cakir discloses the system of claim 8. Cakir does not specifically disclose wherein the one or more language-based ML models are remote to the data processing system. However, Spaner, in the same field of endeavor, discloses wherein the one or more language-based ML models are remote to the data processing system (Spaner, para 0050, the computing device 26 may share the causal graphs with an off-premise (e.g., stored in the cloud and executed by one or more remote computing devices) machine-learning algorithm, large language model, artificial intelligence). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of Spaner in the method of Cakir because this would enable providing improved techniques for identifying root causes within complex industrial automation systems (Spaner, para 0003). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MULUGETA T. DUGDA whose telephone number is (703)756-1106. The examiner can normally be reached Mon - Fri, 4:30am - 7:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Paras D. Shah can be reached at 571-270-1650. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MULUGETA TUJI DUGDA/Examiner, Art Unit 2653 /Paras D Shah/Supervisory Patent Examiner, Art Unit 2653 04/25/2026 Application/Control Number: 18/896,267 Page 2 Art Unit: 2653 Application/Control Number: 18/896,267 Page 3 Art Unit: 2653 Application/Control Number: 18/896,267 Page 4 Art Unit: 2653 Application/Control Number: 18/896,267 Page 5 Art Unit: 2653 Application/Control Number: 18/896,267 Page 6 Art Unit: 2653 Application/Control Number: 18/896,267 Page 7 Art Unit: 2653 Application/Control Number: 18/896,267 Page 8 Art Unit: 2653 Application/Control Number: 18/896,267 Page 9 Art Unit: 2653 Application/Control Number: 18/896,267 Page 10 Art Unit: 2653 Application/Control Number: 18/896,267 Page 11 Art Unit: 2653 Application/Control Number: 18/896,267 Page 12 Art Unit: 2653 Application/Control Number: 18/896,267 Page 13 Art Unit: 2653 Application/Control Number: 18/896,267 Page 14 Art Unit: 2653 Application/Control Number: 18/896,267 Page 15 Art Unit: 2653 Application/Control Number: 18/896,267 Page 16 Art Unit: 2653 Application/Control Number: 18/896,267 Page 17 Art Unit: 2653 Application/Control Number: 18/896,267 Page 18 Art Unit: 2653 Application/Control Number: 18/896,267 Page 19 Art Unit: 2653 Application/Control Number: 18/896,267 Page 20 Art Unit: 2653 Application/Control Number: 18/896,267 Page 21 Art Unit: 2653 Application/Control Number: 18/896,267 Page 22 Art Unit: 2653 Application/Control Number: 18/896,267 Page 23 Art Unit: 2653 Application/Control Number: 18/896,267 Page 24 Art Unit: 2653 Application/Control Number: 18/896,267 Page 25 Art Unit: 2653 Application/Control Number: 18/896,267 Page 26 Art Unit: 2653 Application/Control Number: 18/896,267 Page 27 Art Unit: 2653 Application/Control Number: 18/896,267 Page 28 Art Unit: 2653 Application/Control Number: 18/896,267 Page 29 Art Unit: 2653 Application/Control Number: 18/896,267 Page 30 Art Unit: 2653 Application/Control Number: 18/896,267 Page 31 Art Unit: 2653 Application/Control Number: 18/896,267 Page 32 Art Unit: 2653 Application/Control Number: 18/896,267 Page 33 Art Unit: 2653 Application/Control Number: 18/896,267 Page 34 Art Unit: 2653 Application/Control Number: 18/896,267 Page 35 Art Unit: 2653 Application/Control Number: 18/896,267 Page 36 Art Unit: 2653
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