Office Action Predictor
Last updated: April 16, 2026
Application No. 18/896,323

MEMORY SYSTEM INCLUDING SYSTEM DATA AREA AND USER DATA AREA ALLOCATED BASED ON BAD BLOCK LOCATION

Final Rejection §102
Filed
Sep 25, 2024
Examiner
VERBRUGGE, KEVIN
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
Sk Hynix INC.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
2y 1m
To Grant
83%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
505 granted / 570 resolved
+33.6% vs TC avg
Minimal -6% lift
Without
With
+-5.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
14 currently pending
Career history
584
Total Applications
across all art units

Statute-Specific Performance

§101
4.2%
-35.8% vs TC avg
§103
37.2%
-2.8% vs TC avg
§102
22.3%
-17.7% vs TC avg
§112
8.0%
-32.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 570 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment This final Office action is in response to the amendment filed 12/31/25 which amended claim 19. Claims 1-20 remain pending. The claim 19 rejection is repeated and made final and Applicant’s arguments regarding the amended claim 19 are addressed below. Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 5/28/24. A certified copy of the Korean application has now been retrieved as of 1/6/26. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 19 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication 2005/0144516 to GONZALEZ et al. (which incorporates U.S. Patent Application Publication 2003/0065899 to GOROBETS). GONZALEZ shows the claimed memory system in Fig. 1 for example. He shows the claimed memory device as nonvolatile memory array 103 in Fig. 1, detailed in Fig. 4a. He shows the claimed system data area, user data area, and reserved area as the various areas in Fig. 4a (reserved, zones, spares). The various areas in Fig. 4a are analogous to the claimed areas as follows. The claimed system data area is met by GONZALEZ’s reserved area or any one or more of his zones, if system data is stored therein, since system data can be stored in any of these places as taught in 0059 (which references U.S. Patent Application Publication 2003/0065899 to GOROBETS, who teaches that system data can be stored in any block – see Fig. 4B for example). Further evidence of GONZALEZ’s reserved area being used for system data is found in 0031 where he teaches that “For example, a special ‘reserved’ section can be set aside to store information such as system and device parameters, and information about zone alignment.” The claimed user data area is met by any one or more of GONZALEZ’s zones if user data is stored therein. The claimed reserved area is met by GONZALEZ’s reserved area, or alternatively by his spares area. Each area includes plural memory blocks constituting a plurality of super blocks (what GONZALEZ calls metablocks, a term that is analogous to “super blocks” as taught at 0010) as shown in Figs. 5-10 and 22, for example. He shows the claimed controller as controller 104. GONZALEZ’s controller performs the claimed bad block management operation by determining a bad block (shown in Figs. 5-10 as defects and in Fig. 22 as bad blocks). His controller performs the claimed operation of replacing the bad block with an operable block from a block in a system data area, as claimed, whenever the chosen replacement block is located in a metablock (super block) that is located in a zone storing system data. In other words, GONZALEZ makes no restriction on where the replacement blocks can come from, so in the case where the replacement block is located in a metablock storing system data, the last claim limitation is met. Allowable Subject Matter Claims 1-18 are allowed. Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments regarding amended claim 19 have been considered but are not persuasive. At page 8, second full paragraph, Applicant argues that “the Office alleges that GONZALEZ shows an operation of changing at least one super block allocation from the reserved area to the user data area. See pages 3-5 of the Office action mailed October 1, 2025.” This is not accurate. The Examiner had argued (and still asserts, as seen in the repeated rejection above) that “The claimed system data area is met by GONZALEZ’s reserved area or any one or more of his zones, if system data is stored therein, since system data can be stored in any of these places as taught in 0059” and “His controller performs the claimed operation of replacing the bad block with an operable block from a block in a system data area, as claimed, whenever the chosen replacement block is located in a metablock (super block) that is located in a zone storing system data. In other words, GONZALEZ makes no restriction on where the replacement blocks can come from, so in the case where the replacement block is located in a metablock storing system data, the last claim limitation is met.” To summarize, since GONZALEZ allows system data to be stored in any of the zones 0-N shown in Fig. 4a, then whenever system data is stored in a superblock (metablock) in any of these zones, that that superblock can be considered a system data area (since there is no more-specific definition of system data area other than an area that stores system data, which is certainly met by a superblock storing system data). Then, as shown by GONZALEZ in Figs. 5-10 and 22, when a bad block occurs, it can be replaced with a good block from another superblock, including from a superblock in a system data area. Therefore the arguments are not persuasive and the rejection of claim 19 is maintained and made final. Note It is noted that any citations to specific pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214. Any response to this Office action should be labeled appropriately (including serial number, Art Unit 2132, and type of response) and mailed to Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450; hand-carried or delivered to the Customer Service Window at the Knox Building, 501 Dulany Street, Alexandria, VA 22314; faxed to (571) 273-8300; or filed electronically using the Patent Center. Information regarding the status of published or unpublished applications may be obtained from the Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about the Patent Center and visit https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Kevin Verbrugge/ Kevin Verbrugge Primary Examiner Art Unit 2132
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Prosecution Timeline

Sep 25, 2024
Application Filed
Sep 30, 2025
Non-Final Rejection — §102
Dec 31, 2025
Response Filed
Jan 16, 2026
Final Rejection — §102
Apr 09, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
83%
With Interview (-5.6%)
2y 1m
Median Time to Grant
Moderate
PTA Risk
Based on 570 resolved cases by this examiner. Grant probability derived from career allow rate.

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