DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 3,8,10-15,17 and 21 is/are allowed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 2, 4-7, 9, 16 and 18-20 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1, 4 and 14-16 of U.S. Patent No. 12124367. Although the claims at issue are not identical, they are not patentably distinct from each other.
Pat. No. 12124367
Present application
1. A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: access, as part of a memory management operation, a first bit of a first validity table that indicates whether each physical address of a first set of physical addresses stores valid data, wherein each bit of a plurality of bits of a second validity table indicates whether a respective physical address of the first set of physical addresses stores valid data; transfer, as part of the memory management operation and based at least in part on accessing the first bit of the first validity table, data stored at the first set of physical addresses to a second set of physical addresses; and update, based at least in part on the memory management operation, a second bit of the first validity table that indicates whether each physical address of the second set of physical addresses stores valid data based at least in part on transferring the data.
2. A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: access a bit of a first validity table that indicates whether each physical address of a set of physical addresses stores valid data; and determine whether to access a second validity table in response to determining whether the bit in the first validity table indicates that data stored at the set of physical addresses is valid or invalid.
4. The memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to: transfer data stored at the set of physical addresses to a second set of physical addresses in response to determining that the first validity table indicates valid data for the set of physical addresses and accessing the first validity table; and update the first validity table in response to transferring the data.
5. The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:access a plurality of bits of the second validity table in response to determining that the bit in the first validity table indicates that the data stored at the set of physical addresses is invalid, wherein each bit of the plurality of bits of the second validity table indicates whether a respective physical address of the set of physical addresses stores valid data.
4. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine that the first bit of the first validity table indicates that that one or more physical addresses of the first set of physical addresses are storing invalid data based at least in part on accessing the first bit; access the plurality of bits of the second validity table based at least in part on determining that one or more memory cells sets of the first set of physical addresses are storing invalid data; and identify a subset of the first set of physical addresses that store valid data based at least in part on the plurality of bits of the second validity table, wherein transferring the data further comprises transferring data stored by the subset of the first set of physical addresses to the second set of physical addresses based at least in part on the identifying.
6. The memory system of claim 5, wherein the processing circuitry is further configured to cause the memory system to: determine whether to transfer data for each bit of the plurality of bits based at least in part on a value of each bit of the plurality of bits; and transfer data stored at a subset of the set of physical addresses to a second set of physical addresses in response to determining that each bit of the subset of the plurality of bits indicates that the respective physical address stores valid data.
14. The memory system of claim 1, wherein a first block comprises the first set of physical addresses and a second block comprises the second set of physical addresses.
7. The memory system of claim 2, wherein a first block comprises the set of physical addresses.
15. The memory system of claim 1, wherein the first bit of the first validity table indicates whether each physical address of the first set of physical addresses stores valid data for a set of sequential logical addresses.
9. The memory system of claim 2, wherein a first bit of the first validity table indicates whether each physical address of the set of physical addresses stores valid data for a set of sequential logical addresses.
16. A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to: access, as part of a memory management operation, a first bit of a first validity table that indicates whether each physical address of a first set of physical addresses of a memory device stores valid data, wherein each bit of a plurality of bits of a second validity table indicates whether a respective physical address of the first set of physical addresses stores valid data; transfer, as part of the memory management operation and based at least in part on accessing the first bit of the first validity table, data stored at the first set of physical addresses to a second set of physical addresses of the memory device; and update, based at least in part on the memory management operation, a second bit of the first validity table that indicates whether each physical address of the second set of physical addresses stores valid data based at least in part on transferring the data.
16. A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to: access a bit of a first validity table that indicates whether each physical address of a set of physical addresses stores valid data; and determine whether to access a second validity table in response to determining whether the bit in the first validity table indicates that data stored at the set of physical addresses is valid or invalid.
18. The non-transitory computer-readable medium of The non-transitory computer-readable medium of wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to: transfer data stored at the set of physical addresses to a second set of physical addresses in response to determining that the first validity table indicates valid data for the set of physical addresses and accessing the first validity table; and update the first validity table in response to transferring the data.
19. The non-transitory computer-readable medium of The non-transitory computer-readable medium of wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to: access a plurality of bits of the second validity table in response to determining that the bit in the first validity table indicates that the data stored at the set of physical addresses is invalid, wherein each bit of the plurality of bits of the second validity table indicates whether a respective physical address of the set of physical addresses stores valid data.
20. The non-transitory computer-readable medium of The non-transitory computer-readable medium of wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to: determine whether to transfer data for each bit of the plurality of bits in response to determining whether each bit of the plurality of bits indicates that the respective physical address stores valid data; and transfer data stored at a subset of the set of physical addresses to a second set of physical addresses in response to determining that each bit of the subset of the plurality of bits indicates that the respective physical address stores valid data.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ke (US 11216381): discloses a data storage device and a data processing system capable of rapidly searching for valid pages of a memory block via multilevel mapping tables.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES J CHOI whose telephone number is (571)270-0605. The examiner can normally be reached MON-FRI: 9AM-5PM EST.
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/CHARLES J CHOI/Primary Examiner, Art Unit 2133