DETAILED ACTION
This Office Action is in response to the communication filed on 09/25/2024.
Claims 1-20 are pending.
Claims 1-20 are rejected.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-20 are objected to because of the following informalities:
The claims recite the term “trusted” without any indications regarding how trust is determined. For example is a memory region or operating system trusted because it has been Verified as authenticate? Verified as complete? Verified as errorless? Able to be executed without error? Signed? Verification of the signature? Currently encrypted? Previously encrypted? Currently contained in a TEE? Previously contained in a TEE?
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “interconnect circuit” in claims 1-16 is a relative term. Independent claims recite, “interconnect circuits” however, the specifications do not explicitly link “interconnect circuits” to “interconnect devices 120-126”, thus the “interconnect circuits” could be interpreted as the “interconnect lines 112-116” because a “circuit” or “bus” is simple a closed loop though which electricity can flow. The term is indefinite because the specification does not clearly redefine the term. Dependent claims are also rejected under the same rationale set forth above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-8, 11-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello (U.S. 20210271604), in view of Dengi (U.S. 20240220626).
Regarding claims 1 and 15,
Cariello discloses: A device comprising: (Cariello [Abstract] Methods, systems, and devices that support efficient upload of firmware from memory are described)
a first interconnect circuit; and (Cariello [0012-0020, 0025-0033, 0041-0048] teaches multiple interconnecting circuits which can be at the page, block, plane or device level)
a security microprocessor coupled to the first interconnect circuit and configured to: (Cariello [0119] teaches microprocessor)
receive an operating system management instruction for a first (Cariello [0012-0020, 0031-0034, 0041-0059, 0068-0071, 0083-0094] teaches loading firmware code (operating system management instructions) into multiple memory pages, blocks and planes (regions) of a memory device and contained within one or more memory devices)
synchronize the operating system management instruction with a second interconnect circuit such that the operating system management instruction is applied to a second (Cariello [0012-0020, 0031-0034, 0041-0059, 0068-0071, 0083-0094] teaches loading firmware code in parallel (synchronize) to multiple memory planes, which are contained within multiple memory pages, which can be contained within multiple memory devices)
the second (Cariello [0012-0020, 0031-0034, 0041-0059, 0068-0071, 0083-0094] teaches a first memory plane can store a first copy and a second memory plane can store a second copy of the firmware)
the second (Cariello [0012-0020, 0031-0034, 0041-0059, 0068-0071, 0083-0094] teaches a first memory plane can store a first copy and a second memory plane can store a second copy of the firmware; A memory device that uses firmware layout may load a copy of the firmware into a memory cache by performing a serial retrieval method in which firmware code is serially read from successive pages)
While Cariello discloses memory regions and operating systems Cariello does not explicitly disclose that the memory regions and the operating systems are: trusted operating systems or trusted memory regions
However, in the same field of endeavor Dengi discloses: trusted operating systems that is associated with trusted memory (Dengi [0021-0041, 0057, 0064, 0071] teaches attestation reports to verify operating system images which are associated with trusted domain TEEs)
Cariello and Dengi are analogous art because they are from the same field of endeavor loading firmware during booting.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Cariello and Dengi before him or her, to modify the method of Cariello to include the TEE’s of Cariello because it will provide a way to secure a booting process.
The motivation for doing so would be [“ To address these and other issues, subject matter described herein provides technology and methods to perform secure boot using parallelization”] (Paragraph 0031 by Dengi)].
Therefore, it would have been obvious to combine Cariello and Dengi to obtain the invention as specified in the instant claim.
Regarding claim 8,
Cariello additionally discloses: A system, comprising: (Cariello [Abstract] Methods, systems, and devices that support efficient upload of firmware from memory are described) a second interconnect circuit configured to receive the operating system management instruction from the first interconnect circuit and apply the operating system management instruction to a second trusted operating system (Cariello [0012-0020, 0031-0034, 0041-0059, 0068-0071, 0083-0094] teaches loading firmware code in parallel (synchronize) to multiple memory planes, which are contained within multiple memory pages, which can be contained within multiple memory devices)
Regarding claim 15,
Cariello additionally discloses: A method comprising: (Cariello [Abstract] Methods, systems, and devices that support efficient upload of firmware from memory are described)
Regarding claims 4, 11, and 18,
Cariello in view of Dengi discloses: The device of claim 1, wherein the first interconnect circuit is configured to receive the operating system management instruction from a host driver. (Cariello [Abstract, 0012-0014, 0026-0034, 0048-0058] teaches retrieval of the firmware image form memory (host))
Regarding claims 5, 12, and 19,
Cariello in view of Dengi discloses: The device of claim 4, wherein the first interconnect circuit is configured to send, to the host driver, a notification indicating that the operating system management instruction has been executed for both the first trusted operating system and the second trusted operating system. (Cariello [0069-0082, Fig. 5-550] teaches a notification system which provides an indication whether the firmware has been properly executed)
Regarding claims 6, 13, and 20,
Cariello in view of Dengi discloses: The device of claim 1, wherein: the operating system management instruction comprises an instruction to load the first trusted operating system; and the first interconnect circuit is configured to request that the second interconnect circuit load the second trusted operating system. (Cariello [Abstract, 0012-0014, 0031-0044, 0048-0058] teaches retrieval of operating systems upon start-up)
Regarding claims 7 and 14,
Cariello in view of Dengi discloses: The device of claim 1, wherein: the operating system management instruction comprises an instruction to reset the first (Cariello [Abstract, 0012-0014, 0031-0044, 0058-0065] teaches retrieval of operating systems upon reboot)
Cariello does not explicitly disclose: trusted operating systems
However, in the same field of endeavor Dengi discloses: trusted operating systems (Dengi [0021-0041, 0057, 0064, 0071] teaches attestation reports to verify operating system images which are associated with trusted domain TEEs)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with Dengi for similar reasons as cited in claim 1.
Claims 2-3, 9-10, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello (U.S. 20210271604), in view of Dengi (U.S. 20240220626), and in further view of McElheny (U.S. 20180176006).
Regarding claims 2, 9, and 16,
While Cariello in view of Dengi discloses: The device of claim 1, wherein: the first interconnect circuit comprises a first (Cariello [0012-0020, 0025-0033, 0041-0048] teaches multiple interconnecting circuits which can be at the page, block, plane or device level)
While Cariello in view of Dengi discloses stacked memory and memory dies Cariello in view of Dengi does not explicitly disclose that the dies are: interposer dies
However, in the same field of endeavor McElheny discloses: interposer die (McElheny [0008-0017, 0066-0085] on-memory integrated circuit die for processing including an active interposer mounted on the package substrate)
Cariello in view of Dengi and McElheny are analogous art because they are from the same field of endeavor interconnected circuits.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Cariello in view of Dengi and McElheny before him or her, to modify the secure boot loading of Cariello in view of Dengi to include the programmable devices with off-chip memory of McElheny because it will improved speed and reduced energy consumption.
The motivation for doing so would be [“ improv speed and reduce energy consumptions”] (Paragraph 0004, 0077, 0085 by McElheny)].
Therefore, it would have been obvious to combine Cariello in view of Dengi and McElheny to obtain the invention as specified in the instant claim.
Regarding claims 3, 10, and 17,
Cariello in view of Dengi discloses: The device of claim 2, wherein:
Cariello in view of Dengi does not explicitly disclose: the first interposer die comprises a first active interposer die; and the second interposer die comprises a second active interposer die.
However, in the same field of endeavor McElheny discloses: the first interposer die comprises a first active interposer die; and the second interposer die comprises a second active interposer die. (McElheny [0008-0017, 0066-0085] on-memory integrated circuit die for processing including an active interposer mounted on the package substrate)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify with McElheny for similar reasons as cited in claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure.
Liang 2013-6-24 (US 20140331033) teaches a firmware code loading method for loading a firmware code from a rewritable non-volatile memory module of a memory storage apparatus is provided. The method includes: obtaining a storage address for storing a first portion firmware code copy corresponding to a first portion of the firmware code in a first memory part; and obtaining a storage address for storing a second portion firmware code copy corresponding to a second portion of the firmware code in a second memory part. The method further includes: using a parallel mode or a interleave mode to load the first portion firmware code copy and the second portion firmware code copy respectively from the first memory part and the second memory part into a buffer memory. Accordingly, the method can effectively shorten the time of loading the firmware code.
Kim 2021-10-17 (US 20220130841) A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.
Dewan 2020-03-27 (US 20210303691) teaches an apparatus to implement an IP independent firmware load is disclosed. The apparatus includes a plurality of agents, a plurality of agents, at least one agent including a memory to store firmware to be executed by the agent to perform a function associated with the agent and a register to store enumeration data for the firmware load mechanism of the IP, and a processor to initiate an enumeration process to read the enumeration data from the register of the at least one agent, make a decision based on that data to retrieve a firmware module from a storage device, verify the firmware module, and load the firmware module into the memory of the at least one agent.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS A CARNES whose telephone number is (571)272-4378. The examiner can normally be reached Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shewaye Gelagay can be reached at (571) 272-4219. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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THOMAS A. CARNES
Examiner
Art Unit 2436
/THOMAS A CARNES/Examiner, Art Unit 2436 /SHEWAYE GELAGAY/Supervisory Patent Examiner, Art Unit 2436