Prosecution Insights
Last updated: July 17, 2026
Application No. 18/896,425

CONNECTION CIRCUIT

Final Rejection §103
Filed
Sep 25, 2024
Priority
Sep 25, 2023 — DE 10 2023 125 834.6
Examiner
PHAM, DUC M
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Eberspächer Controls Landau GmbH & Co. Kg
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
557 granted / 630 resolved
+20.4% vs TC avg
Moderate +13% lift
Without
With
+12.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
20 currently pending
Career history
672
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
77.6%
+37.6% vs TC avg
§102
14.7%
-25.3% vs TC avg
§112
0.8%
-39.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 630 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This office action is a response to a paper filed on 12/31/2025 in which claims 1-20 are pending and ready for examination. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 18-24 and 27-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo Calzo et al (hereinafter Lo Calzo) (US 2024/0001767 A1) in view of Okada et al (hereinafter Okada) (US 2013/0229151 A1). As to claims 18 and 36, Lo Calzo discloses a connection circuit for connecting a plurality of consumers (Fig 6, 11, 30) of electrical energy to a direct current source (Fig 6, 6, 10), the connection circuit comprising: a plurality of connection switches (Fig 6, 23), each consumer of electrical energy of said plurality of consumers of electrical energy having associated therewith one connection switch of said plurality of connection switches for establishing a connection thereof to said direct current source (Fig 6, 6, 10); connection switch activation circuits (Fig 10, two control units 21), each consumer of electrical energy of said plurality of consumers (Fig 6, 11, 30) of electrical energy having associated therewith one connection switch activation circuit of said plurality of connection switch activation circuits for supplying a current thereto and for activating the connection switch thereof in order to establish the connection thereof to said direct current source (see Fig 6, parags [0052-0055], a selection unit 22 configured to selectively connect or disconnect certain loads 11 according to the commands given by the control unit 21). Lo Calzo does not disclose plurality of connection switch activation circuits. However, Lo Calzo does disclose two control units (Fig 10, 21). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the control units of Lo Calzo to become plurality of control units in order to control power provided to plurality of loads. In re Dulberg, 289 F.2d 522, 523, 129 USPQ 348, 349 (CCPA 1961). Lo Calzo does not disclose wherein each one of the connection switch activation circuits includes a switching transistor, wherein a base-emitter voltage of the switching transistor depends on the current supplied to the associated consumer via the corresponding connection switch activation circuit; and, wherein, when a base-emitter voltage at a collector terminal of the switching transistor exceeds a threshold voltage, a switch signal is generated for switching the associated connection switch into a closed state that establishes a connection between the associated consumer and the direct current source. However, Okada discloses wherein a switch activation circuit (Fig 2, 8) includes a switching transistor (Fig 2, T8), wherein a base-emitter voltage of the switching transistor depends on the current supplied to the associated consumer via the corresponding connection switch activation circuit; and, wherein, when a base-emitter voltage at a collector terminal of the switching transistor exceeds a threshold voltage, a switch signal is generated for switching the associated connection switch into a closed state that establishes a connection between the associated consumer and the direct current source (see Fig 2, functions of a NPN transistor). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the control unit of Lo Calzo with a NPN transistor as taught by Okada in order to control the connection of the load based on the transistor. As to claim 19, the combination of Lo Calzo and Okada discloses the connection circuit of claim 18, wherein each connection switch activation circuit of said plurality of connection switch activation circuits includes a diode circuit having a reference diode (Okada, Fig 2, ZD); and, the base-emitter voltage of the switching transistor is related to a voltage drop at the reference diode in the diode circuit (Okada, see parag [0047]). As to claim 20, the combination of Lo Cazlo and Okada discloses the connection circuit of claim 19, wherein the base-emitter voltage corresponds to a voltage drop at the reference diode (Okada, see parag [0043]). As to claim 21, the combination of Lo Cazlo and Okada discloses the connection circuit of claim 20, wherein the reference diode is a p-n diode (Okada, see Fig 2, ZD). As to claim 22, the combination of Lo Calzo and Okada does not disclose the connection circuit of claim 20, wherein the reference diode is a silicon diode. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to modify the diode of Lo Calzo and Okada to become a silicon diode in order to achieve better connection, since this is just a designed choice and involves only routine skills in the art. As to claim 23, the combination of Lo Calzo and Okada discloses the connection circuit of claim 19, wherein the diode circuit has at least one electrical resistor (Fig 2, R) connected in series with the reference diode (Fig 2, ZD), and wherein the base-emitter voltage substantially corresponds to a voltage drop at the series connection of the reference diode and at least one electrical resistor. As to claim 24, the combination of Lo Calzo and Okada does not disclose the connection circuit as claimed in claim 23, wherein the reference diode is a Schottky diode or a germanium diode. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to modify the diode or Lo Calzo and Okada to become a Schottky or Germanium diode in order to achieve better performance. As to claim 27, the combination of Lo Calzo and Okada discloses the connection circuit of claim 18, wherein the connection switch activation circuit has a control signal circuit (Lo Calzo, see Fig 2, 21); wherein the control signal circuit is configured to generate, when a switch signal has been generated at the collector terminal of the connection switch activation circuit, a control signal to be applied at the associated connection switch for switching the connection switch into the closed state thereof (see parag [0052]). As to claim 28, the combination of Lo Calzo and Okada discloses the connection switch of claim 18, wherein the connection switch activation circuit has an input terminal which is connected or is to be connected to the direct current source, and an output terminal which is connected or is to be connected to the associated consumer of electrical energy (see Fig 2 configuration). As to claim 29, the combination of Lo Calzo and Okada discloses the connection circuit of claim 19, wherein the reference diode (Fig 2, 26) is connected in a forward direction between the input terminal and the output terminal. As to claim 30, the combination of Lo Calzo and Okada discloses the connection circuit of claim 28, wherein at least one of the following applies: i) an emitter terminal of the switching transistor is connected to the input terminal; and, ii) a base terminal of the switching transistor is connected to the output terminal (Okada, see Fig 2, ZD). As to claim 31, the combination of Lo Calzo and Okada discloses the connection circuit of claim 28, wherein a safety circuit (Fig 6, 26) is provided, wherein the input terminals of all connection switch activation circuits (Fig 6, 20) are connected or are to be connected via a safety circuit to the direct current sources (Fig 6, 6, 10); wherein the safety circuit is configured to monitor the current from the direct current source to all of the consumers; and, wherein the current exceeds a threshold current, to interrupt the connection between the direct current source and all of the consumers (see Fig 6, the circuit 20 will deactivate diode 26 to disconnect the direct current sources 6, 10 and loads 11, 30). As to claim 32, the combination of Lo Calzo and Okada discloses the connection circuit of claim 18, wherein a connection circuit activation unit is provided, wherein the connection circuit activation unit, when the switch signal is generated by at least one connection switch activation circuit associated with one consumer, performs at least one of the following: i) deactivates all connection switch activation circuits; ii) switches at least some of the connection switches into the closed state thereof (Lo Calzo, see parag [0052]); and, iii) switches all connection switches into the closed state thereof. As to claim 33, the combination of Lo Calzo and Okada discloses the connection circuit of claim 31, wherein the connection switch activation unit is configured, in order to deactivate all connection switch activation circuits, to switch the safety circuit into an interrupt state interrupting the connection between the direct current source and all of the consumers (see Fig 6, the circuit 20 will deactivate diode 26 to disconnect the direct current sources 6, 10 and loads 11, 30). As to claim 34, the combination of Lo Calzo and Okada discloses the connection circuit of claim 18, wherein the switching transistor is a bipolar transistor (Okada, see Fig 2, ZD). As to claim 35, the combination of Lo Calzo and Okada discloses the connection circuit of claim 18, wherein said connection circuit is in a vehicle (Lo Calzo, see parag [0031]). Allowable Subject Matter Claims 25-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: As to claim 25, the cited prior arts alone or in combination fail to disclose: “wherein the diode circuit has a load diode connected in parallel to the reference diode”. Claim 37 is allowed. The following is an examiner’s statement of reasons for allowance: As to claim 37, the cited prior arts alone or in combination fail to disclose:“wherein the connection switch activation circuit includes a diode circuit having a reference diode; and, the base-emitter voltage of the switching transistor is related to a voltage drop at the reference diode in the diode circuit; and wherein the diode circuit has a load diode connected in parallel to the reference diode”. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant’s arguments, see pages 1-3, filed on 12/31/2025, with respect to the rejection(s) of claim(s) 18, 36 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lo Calzo and Okada. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUC M PHAM whose telephone number is (571)272-5026. The examiner can normally be reached 10:00 am - 6:00 pm, Monday to Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kim, Taelor can be reached at 571-270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUC M PHAM/Examiner, Art Unit 2836 May 27, 2026 /DANIEL C PUENTES/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Sep 25, 2024
Application Filed
Oct 01, 2025
Non-Final Rejection mailed — §103
Dec 31, 2025
Response Filed
Jun 01, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.7%)
2y 4m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 630 resolved cases by this examiner. Grant probability derived from career allowance rate.

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