DETAILED ACTION
The instant application having Application No. 18/896,431 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-2, 4, 8-10, 12, and 16-19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Graif et al. (Publication Number US 2019/0108149 A1) in view of Ramaraju et al. (Publication Number US 2013/0046928 A1).
As per claim 1, Graif et al. discloses “A system comprising: a first device comprising: a first register configured to store a first address (see bus master with address table 412 that contains an entry 414 with several fields (‘Device’, ‘StAdr’, ‘DynAdr’); FIG. 4; Paragraph 0055).” Graif et al. discloses “a second register configured to store a first device identifier (example is the static address 430a, 430b; FIG. 4; Paragraph 0055).” Graif et al. discloses “a third register configured to store a value, [the value adapted to be a logical AND of the first device identifier and a second device identifier] (example is the assigned dynamic address 424; FIG. 4; Paragraph 0055).”
Graif et al. discloses “and after determining the second address, the first circuit sets the first register to store the second address (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
Graif et al. discloses “and a second device comprising: a fourth register configured to store the first address (see bus master with address table 412 that contains an entry 414 with several fields (‘Device’, ‘StAdr’, ‘DynAdr’) [FIG. 4; Paragraph 0055]. Note the presence of a table with ‘entries’).” Graif et al. discloses “a fifth register configured to store the second device identifier (example is the static address 430a, 430b; FIG. 4; Paragraph 0055).” Graif et al. discloses “a sixth register configured to store the value (example is the assigned dynamic address 424; FIG. 4; Paragraph 0055).”
Graif et al. discloses “and after determining the third address, the second circuit sets the fourth register to store the third address (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
However, Graif et al. does not disclose “the value adapted to be a logical AND of the first device identifier and a second device identifier,” “and a first circuit coupled to the first register, the second register, and the third register, the first circuit configured to: determine the second device identifier based on the first device identifier of the second register and the value of the third register,” “responsive to determining the second device identifier, the first circuit compares the first device identifier to the second device identifier,” “after comparing the first device identifier to the second device identifier, the first circuit determines a second address,” “and a second circuit coupled to the fourth register, the fifth register, and the sixth register, the second circuit configured to: determine the first device identifier based on the second device identifier of the fifth register and the value of the sixth register,” “responsive to determining the first device identifier, the second circuit compares the first device identifier to the second device identifier,” or “after comparing the first device identifier to the second device identifier, the second circuit determines a third address.”
Ramaraju et al. discloses “the value adapted to be a logical AND of the first device identifier and a second device identifier (a G value results from a logical AND operation on each address bit pair; Paragraph 0061).”
Ramaraju et al. discloses “and a first circuit coupled to the first register, the second register, and the third register, the first circuit configured to: determine the second device identifier based on the first device identifier of the second register and the value of the third register (where Z value results from a logical AND operation performed on each…address bit pair; Paragraph 0061).” Ramaraju et al. discloses “responsive to determining the second device identifier, the first circuit compares the first device identifier to the second device identifier (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).” Ramaraju et al. discloses “after comparing the first device identifier to the second device identifier, the first circuit determines a second address (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).”
Ramaraju et al. discloses “and a second circuit coupled to the fourth register, the fifth register, and the sixth register, the second circuit configured to: determine the first device identifier based on the second device identifier of the fifth register and the value of the sixth register (a G value results from a logical AND operation on each address bit pair; Paragraph 0061).” Ramaraju et al. discloses “responsive to determining the first device identifier, the second circuit compares the first device identifier to the second device identifier (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).” Ramaraju et al. discloses “after comparing the first device identifier to the second device identifier, the second circuit determines a third address (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Graif et al. and Ramaraju et al. to address improved memory access [Paragraph 0006].
As per claim 2, Graif et al. discloses “The system of claim 1 (as disclosed by Graif et al. and Ramaraju et al. above), wherein the value is a first value, the first device includes a seventh register and a second value, the seventh register is configured to store the second value (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
Ramaraju et al. discloses “and the second value is representative of a logical AND of an inverse of the first device identifier and an inverse of the second device identifier (see inverted address bit pair; Paragraph 0061).”
As per claim 4, Graif et al. discloses “The system of claim 1 (as disclosed by Graif et al. and Ramaraju et al. above), wherein the value is a first value, the second device includes a seventh register and a second value, the seventh register is configured to store the second value (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
Ramaraju et al. discloses “and the second value is representative of a logical AND of an inverse of the first device identifier and an inverse of the second device identifier (see inverted address bit pair; Paragraph 0061).”
As per claims 8 and 16, Graif et al. discloses “The system of claim 1 (as disclosed by Graif et al. and Ramaraju et al. above), wherein the first device and the second device communicate using I2C communication (Paragraph 0045).”
As per claim 9, Graif et al. discloses “A method comprising: storing, by a first register of a first device, a first address (see bus master with address table 412 that contains an entry 414 with several fields (‘Device’, ‘StAdr’, ‘DynAdr’); FIG. 4; Paragraph 0055).”
Graif et al. discloses “storing, by a second device, the first address in a fourth register of the second device (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
Graif et al. discloses “after determining the second address, setting, by the first circuit, the first register to store the second address (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).” Graif et al. discloses “and storing, by the fourth register, the third address (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
However, Graif et al. does not disclose “determining, by a first circuit of the first device, a second device identifier based on a first device identifier in a second register of the first device and a value of a third register of the first device,” “responsive to determining the second device identifier, comparing, by the first circuit, the first device identifier to the second device identifier,” “after comparing the first device identifier to the second device identifier, determining, by the first circuit, a second address,” “determining, by a second circuit of the second device, the first device identifier based on the second device identifier in a fifth register of the second device and the value in a sixth register of the second device,” “responsive to determining the first device identifier, comparing, by the second circuit of the second device, the first device identifier to the second device identifier,” and “after comparing the first device identifier to the second device identifier, determining, by the second circuit of the second device, a third address.”
Ramaraju et al. discloses “determining, by a first circuit of the first device, a second device identifier based on a first device identifier in a second register of the first device and a value of a third register of the first device (where Z value results from a logical AND operation performed on each…address bit pair; Paragraph 0061).” Ramaraju et al. discloses “responsive to determining the second device identifier, comparing, by the first circuit, the first device identifier to the second device identifier (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).” Ramaraju et al. discloses “after comparing the first device identifier to the second device identifier, determining, by the first circuit, a second address (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).” Ramaraju et al. discloses “determining, by a second circuit of the second device, the first device identifier based on the second device identifier in a fifth register of the second device and the value in a sixth register of the second device (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).” Ramaraju et al. discloses “responsive to determining the first device identifier, comparing, by the second circuit of the second device, the first device identifier to the second device identifier (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).” discloses “after comparing the first device identifier to the second device identifier, determining, by the second circuit of the second device, a third address (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Graif et al. and Ramaraju et al. to address improved memory access [Paragraph 0006].
As per claim 10, Graif et al. discloses “The method of claim 9 (as disclosed by Graif et al. and Ramaraju et al. above), wherein the value is a first value, the method further comprising storing a second value in a seventh register of the first device (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
Ramaraju et al. discloses “wherein the second value is representative of a logical AND of an inverse of the first device identifier and an inverse of the second device identifier (see inverted address bit pair; Paragraph 0061).”
As per claim 12, Graif et al. discloses “The method of claim 9 (as disclosed by Graif et al. and Ramaraju et al. above), wherein the value is a first value, the method further comprising, storing, in a seventh register of the second device, a second value (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
Ramaraju et al. discloses “wherein the second value is representative of a logical AND of an inverse of the first device identifier and an inverse of the second device identifier (see inverted address bit pair; Paragraph 0061).”
As per claim 17, Graif et al. discloses “A system comprising: a device comprising: a first register configured to store a first address (see bus master with address table 412 that contains an entry 414 with several fields (‘Device’, ‘StAdr’, ‘DynAdr’); FIG. 4; Paragraph 0055).” Graif et al. discloses “a second register configured to store a first device identifier (example is the static address 430a, 430b; FIG. 4; Paragraph 0055).”
Graif et al. discloses “and after determining the second address, the first circuit sets the first register to store the second address (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
However, Graif et al. does not disclose “a third register configured to store a value, the value adapted to be a logical AND of the first device identifier and a second device identifier,” “and a circuit coupled to the first register, the second register, and the third register, the circuit configured to: determine the second device identifier based on the first device identifier of the second register and the value of the third register,” “responsive to determining the second device identifier, the first circuit compares the first device identifier to the second device identifier,” or “after comparing the first device identifier to the second device identifier, the first circuit determines a second address.” Ramaraju et al. discloses “a third register configured to store a value, the value adapted to be a logical AND of the first device identifier and a second device identifier (a G value results from a logical AND operation on each address bit pair; Paragraph 0061).” Ramaraju et al. discloses “and a circuit coupled to the first register, the second register, and the third register, the circuit configured to: determine the second device identifier based on the first device identifier of the second register and the value of the third register (where Z value results from a logical AND operation performed on each…address bit pair; Paragraph 0061).” Ramaraju et al. discloses “responsive to determining the second device identifier, the first circuit compares the first device identifier to the second device identifier (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).” Ramaraju et al. discloses “after comparing the first device identifier to the second device identifier, the first circuit determines a second address (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Graif et al. and Ramaraju et al. to address improved memory access [Paragraph 0006].
As per claim 18, Graif et al. discloses “The system of claim 17 (as disclosed by Graif et al. and Ramaraju et al. above), wherein the device is a first device and the circuit is a first circuit, the system further comprising: a second device comprising: a fourth register configured to store the first address (see bus master with address table 412 that contains an entry 414 with several fields (‘Device’, ‘StAdr’, ‘DynAdr’); FIG. 4; Paragraph 0055).” Graif et al. discloses “a fifth register configured to store the second device identifier (example is the static address 430a, 430b; FIG. 4; Paragraph 0055).” Graif et al. discloses “a sixth register configured to store the value (example is the static address 430a, 430b; FIG. 4; Paragraph 0055).” Graif et al. discloses “and after determining the third address, the second circuit sets the fourth register to store the third address (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
Ramaraju et al. discloses “and a second circuit coupled to the fourth register, the fifth register, and the sixth register, the second circuit configured to: determine the first device identifier based on the second device identifier of the fifth register and the value of the sixth register (a G value results from a logical AND operation on each address bit pair; Paragraph 0061).” Ramaraju et al. discloses “responsive to determining the first device identifier, the second circuit compares the first device identifier to the second device identifier (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).” Ramaraju et al. discloses “after comparing the first device identifier to the second device identifier, the second circuit determines a third address (as demonstrated by the use of a selection circuit [Paragraph 0061] indicating that certain values must be examined for a choice to be made).”
As per claim 19, Graif et al. discloses “The system of claim 17 (as disclosed by Graif et al. and Ramaraju et al. above), wherein the value is a first value, the device includes a seventh register and a second value, the seventh register is configured to store the second value (address table 518 that contains entries for devices and their addresses (both static and dynamic); FIG. 5; Paragraph 0056).”
Ramaraju et al. discloses “and the second value is representative of a logical AND of an inverse of the first device identifier and an inverse of the second device identifier (see inverted address bit pair; Paragraph 0061).”
Claims 3, 5-6, 11, 13-14, and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Graif et al. (Publication Number US 2019/0108149 A1) and Ramaraju et al. (Publication Number US 2013/0046928 A1) in view of Keralapura Manjunatha et al. (Foreign Publication Number CA 3 160 683).
As per claims 3, 11, and 20, Graif et al. and Ramaraju et al. disclose “The system of claim 1 (as disclosed by Graif et al. and Ramaraju et al. above).” However, Graif et al. and Ramaraju et al. do not disclose “wherein the first circuit is configured to determine whether the first device identifier is greater than the second device identifier.”
Keralapura Manjunatha et al. discloses “wherein the first circuit is configured to determine whether the first device identifier is greater than the second device identifier (‘if the counter register k is equal to (e.g. equal to or greater than); Paragraph 0072).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Graif et al. and Ramaraju et al. with elements of Keralapura Manjunatha et al. as a means of better calculations and processing that could prevent wasting bandwidth and power resources [Paragraph 0003].
As per claims 5 and 13, Graif et al. and Ramaraju et al. disclose “The system of claim 1 (as disclosed by Graif et al. and Ramaraju et al. above).” However, Graif et al. and Ramaraju et al. do not disclose “wherein the second circuit is configured to determine whether the first device identifier is greater than the second device identifier.”
Keralapura Manjunatha et al. discloses “wherein the second circuit is configured to determine whether the first device identifier is greater than the second device identifier (‘if the counter register k is equal to (e.g. equal to or greater than); Paragraph 0072).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Graif et al. and Ramaraju et al. with elements of Keralapura Manjunatha et al. as a means of better calculations and processing that could prevent wasting bandwidth and power resources [Paragraph 0003].
As per claims 6 and 14, Graif et al. and Ramaraju et al. disclose “The system of claim 1 (as disclosed by Graif et al. and Ramaraju et al. above).” However, Graif et al. and Ramaraju et al. do not disclose “wherein the first address is equal to the third address, and the third address is representative of only the second device.”
Keralapura Manjunatha et al. discloses “wherein the first address is equal to the third address, and the third address is representative of only the second device (‘if the counter register k is equal to (e.g. equal to or greater than); Paragraph 0072).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Graif et al. and Ramaraju et al. with elements of Keralapura Manjunatha et al. as a means of better calculations and processing that could prevent wasting bandwidth and power resources [Paragraph 0003].
Claims 7 and 15 are rejected under 35 U.S.C. 103(a) as being unpatentable over Graif et al. (Publication Number US 2019/0108149 A1) and Ramaraju et al. (Publication Number US 2013/0046928 A1) in view of Decesaris et al. (Publication Number US 2015/0026374 A1).
As per claims 7 and 15, Graif et al. and Ramaraju et al. disclose “The system of claim 1 (as disclosed by as disclosed by Graif et al. and Ramaraju et al. above).” However, Graif et al. and Ramaraju et al. do not disclose “wherein the first device identifier is a first universally unique identifier (UUID) and the second device identifier is a second UUID.”
Decesaris et al. discloses “wherein the first device identifier is a first universally unique identifier (UUID) and the second device identifier is a second UUID (Paragraph 0025).”
Graif et al. and Decesaris et al. are analogous art in that they in the field of I2C/I3C.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Graif et al. and Ramaraju et al. with elements of Decesaris et al. as a means of better identifying individual devices and each device’s characteristics such as manufacturer information [Paragraph 0002].
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated September 25, 2024, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach device addressing/identifying.
U.S. PATENT NUMBERS:7,774,537 B2 – [Column 15, lines 7-40]
CLOSING COMMENTS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS ALROBAYE can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/H.W.Y/Examiner, Art Unit 2181 December 8, 2025
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181