DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Abstract
3. The abstract of the disclosure is acceptable for examination purposes.
Oath Declaration
4. The Oath complies with all the requirements set forth in MPEP 602 and therefore is accepted.
Drawings
5. The drawings received on 09/25/2024 are acceptable for examination purposes.
Interpretation under 35 USC 112(f)
6. Examiner notes that no limitations in instant claims invoke 35 USC 112(f) and those same claims are examined accordingly.
Information Disclosure Statement
7. The references listed in the information disclosure statement (IDS) submitted on 02/05/2025, 03/26/2025, and 05/08/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97. Form PTO- 1449 is signed and attached hereto.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 1-6, 8, and 12-20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Mundada Pranav S. ET AL: "Experimental Benchmarking of an Automated Deterministic Error-Suppression Workflow for Quantum Algorithms", Physical Review Applied, vol. 20, no. 2, 3 May 2023 (2023-05-03) “herein after as Pranav” in view of Arute et al., "Observation of Separated Dynamics of Charge and Spin in the Fermi-Hubbard Model", Google AI Quantum and Collaborators; arXiv:2010.07965v1, October 19, 2020.
As per claim 1:
Pranav substantially teaches or discloses a computer implemented method for characterizing at least one target error parameter of implementation errors in a quantum logic operation g acting on a targeted set of qubits of a quantum processor, the method comprising (see abstract; see page 2, col. 1, Most hardware backends provide tabulated data for the error rate associated with each gate in an algorithm, as measured using device-level characterization protocols such as randomized benchmarking, cycle benchmarking and gateset tomography; and entire pipeline comprising error characterization as part of the error aware compilation and dynamical decoupling techniques, in order to characterize and mitigate errors, wherein said characterization is a result of said error-suppression protocol in Figure 1 , and page 3, col. 1 , last paragraph - page 4, col. 2, first paragraph ; and Fig. 1): (a) generating at least one characterization sequence S configured for amplifying said at least one target error parameter, said at least one characterization sequence S comprises at least one refocusing sequence (see abstract, dynamical decoupling sequences and its staggered variant to mitigate errors, said sequences amplifying and studying error effects such as coherent crosstalk (i.e., characterization sequences) "We introduce the key elements of this work ow, delivered as a software package called Fire Opal, and survey the underlying physical concepts: error-aware compilation, automated system-wide gate optimization, automated dynamical decoupling embedding for circuit-level error cancellation, and calibration- efficient measurement error mitigation.", page 16, col. 2, paragraph 2: "[...] to mitigate ZZ-error, the timings of bit ip on the two qubits need to be staggered and correlated.", page 16, col. 1 , last paragraph: "[...] crosstalk errors due to spurious ZZ coupling can be mitigated by a DD protocol.", wherein DD sequences, by definition suppress unwanted error terms (including crosstalk and idle errors)), wherein the at least one refocusing sequence is configured so that the characterization sequence reduces predefined generator terms including crosstalk between said targeted set of qubits and another set of qubits of the quantum processor (see 2, col. 2, paragraph 3, page 16, col. 1 , last paragraph, and page 15, col. 1 , first paragraph, second bullet; use of dynamical decoupling to mitigate errors such as ZZ crosstalk between qubits, as well as applying these sequences at the algorithmic level with knowledge of errors and device topology (i.e., refocusing sequences reducing predefined generator terms).
Pranav does not explicitly teach characterizing said at least one target error parameter using said at least one characterization sequence in a characterization protocol.
However, Arute in the same the field of endeavor teaches characterizing said at least one target error parameter using said at least one characterization sequence in a characterization protocol (see page 10, col. 1, Calibration of quantum gates is one of the most crucial steps in achieving high-fidelity quantum computation and its large-scale deployment [48–50]. Temporal instabilities, including drifts and fluctuations in the control fields and qubit frequencies [51–58], can propagate and accumulate coherently in large quantum circuits. Therefore, it is crucial to develop fast and accurate calibration methods to characterize and mitigate these errors. However, common calibration tools, such as randomized benchmarking [59, 60], compressed sensing [61, 62], gate set tomography [63, 64], and cross-entropy benchmarking [65] are often too slow to capture drifts and fluctuations in the hardware --- in these respects, our protocol resembles gate set tomography, with the composite gates playing the role of “germs” therein, though by prioritizing the errors we wish to calibrate and leveraging well the form of single-qubit gates we require far fewer resources than is typical for gate set tomography).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Pranav with the teachings of Arute by including characterizing said at least one target error parameter using said at least one characterization sequence in a characterization protocol.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the characterizing said at least one target error parameter using said at least one characterization sequence in a characterization protocol would have improved the quantum computer performance.
As per claim 2:
Pranav teaches that wherein characterizing the at least one target error parameter comprises: (a) applying the at least one characterization sequence S to the quantum processor (see page 3, col. 2 Dynamical decoupling (DD) sequences are incorporated to mitigate various idling errors including dephasing and ZZ crosstalk at the algorithmic level. The underlying pulse sequences are optimized for the specifications of a particular backend via an automatic \ranking" routine. The ranking routine is context-aware, applying optimal sequences to each qubit's idle period with knowledge of single-qubit gate errors as well as the gate sequences applied to neighboring qubits in order to account for both quantum and classical (single-qubit-gate) crosstalk); (b) measuring the targeted set of qubits using a measurement apparatus of said quantum processor, thereby obtaining a set of measurement values; (c) computing a value of said at least one target error parameter, by fitting a model to said set of measurement values (see eliminating crosstalk and mitigating decoherence errors using dynamic decoupling, reducing coherent error terms and improving quantum operations by addressing multiple error types, including gate and measurement errors, wherein a target error parameter is characterized as part of the systemwide optimization and dynamical decoupling processes, in Appendix C, section 2, see Pauli generator terms in the quantum circuit and characterization sequences such as Pauli twirling to mitigate predefined Pauli error terms distinct from the target error parameter, in section C.2 and Appendix A).
As per claim 3:
Pranav teaches that wherein: (a) said at least one characterization sequence S is configured for reducing predefined coherent error generator terms in said targeted set of qubits; (b) the method characterizes a single target error parameter of implementation errors in the quantum logic operation g; (c) said at least one target error parameter is a Pauli generator term P.sub.t; said at least one characterization sequence S is configured to eliminate predefined Pauli generator terms of said implementation errors distinct from the at least one target error parameter; and (d) said at least one refocusing sequence commutes with said Pauli generator term P.sub.t (seepage 16, col. 1 , last paragraph, Dynamical decoupling (DD) is an open-loop quantum control technique aimed at suppressing idling errors. In its simplest form, DD is implemented by periodic sequences of quantum bit flips, whose net effect is to approximately cancel unwanted couplings. Most traditional DD protocols are designed to reduce global dephasing (T2 processes), but different schemes exist for designing DD protocols for specific error-reducing tasks).
As per claim 4:
Pranav teaches that wherein said at least one refocusing sequence is any of: a dynamical decoupling sequence, and a twirling sequence (page 10, col. 2, paragraph 4, see Q-CTRL pipeline in Table Il, and Pauli twirling).
As per claim 5:
Pranav teaches that wherein said at least one characterization sequence S is configured to any of: reducing a magnitude measure of said crosstalk, and eliminating at least a first-order error of implementation errors distinct from the at least one target error parameter (seepage 16, col. 1, last paragraph, most traditional DD protocols are designed to reduce global dephasing (T2 processes), but different schemes exist for designing DD protocols for specific error-reducing tasks [38, 41]. For instance, crosstalk errors due to spurious ZZ coupling can be mitigated by a DD protocol. Yet, protocols that mitigate ZZ errors can change dramatically from one algorithm to another and from one device to another, depending on the device topology, connectivity, and ability to parallelize the different layers of the algorithm.
As per claim 6:
Pranav teaches that wherein the at least one refocusing sequences includes a set of refocusing sequences, and wherein said at least one characterization sequence S comprises at least one recursively concatenated germ obtained by computing a predefined number n of concatenations G.sub.k+1=Π.sub.mG.sub.kβ.sub.m.sup.(k), wherein k=0, 1, . . . , n−1, wherein, β.sub.m.sup.(k) are refocusing sequences included in said set of refocusing sequences and G.sub.0=g, g being said quantum logic operation (see page 2, col. 1, Most hardware backends provide tabulated data for the error rate associated with each gate in an algorithm, as measured using device-level characterization protocols such as randomized benchmarking, cycle benchmarking and gateset tomography [26{32]. These protocols return average proxy measures which characterize the fidelity of single and multi-qubit gates, the building blocks of quantum algorithms (i.e. randomized benchmarking, gate set tomography, or quantum process tomography), said methods not being specific to any physical implementation but instead operating at the logical level of quantum information; the condition that P P and Py span an algebra isomorphic to SU(2) is limiting the characterization process on fundamental algebraic properties of qubit rotations and transformations, independent of any physical implementation of qubits).
As per claim 8:
Pranav teaches that wherein said quantum logic operation g is a two-qubit operation, and wherein: (a) said Pauli generator term P.sub.t anti-commutes with at least one generator of a KAK decomposition of an ideal version of said quantum logic operation g; (b) a sum of coefficients is greater than 3π/4, said coefficients corresponding to said at least one KAK generator anti-commuting with said Pauli generator term P.sub.t; and (c) said at least one refocusing sequence comprises at least one secondary refocusing sequence, said at least one secondary refocusing sequence commuting with all commutators of said Pauli generator term P.sub.t and generators of said KAK decomposition of an ideal version of said quantum logic operation g (see page 9, col. 1 last paragraph, We benchmark the performance of VQE by utilizing it to compute the ground state energy of Beryllium hydride (BeH2) molecule [52], which can be well described (with a minimal loss of precision) by considering four interacting atomic orbitals and a spin degree of freedom, which in turn, can be mapped to a 6-qubit problem. Such a mapping converts the Hamiltonian of the molecule into a sum of multi-qubit Pauli operators over the 6 qubits,(note: Pauli generator terms are generic algebraic terms representing different types of quantum errors (e.g., X,Y,Z errors) applied to any quantum computing model (including logical qubits); recursively concatenated germs with n concatenation steps are a generic RB error amplification technique, wherein the recursive structure and error suppression ratios refer to generic scaling law for error mitigation, and not to any implementation-specific effect; refocusing a sequence that anticommutes with a Pauli generator term is applied to any quantum computing model (including logical qubits); isolating a specific Pauli generator term is a universal error characterization technique applicable to any quantum system, i,e., to a logical qubits' system).
As per claim 12:
Pranav teaches that applied to at least two quantum logic operations in parallel, wherein said at least two quantum logic operations operate on corresponding subsets of qubits, each of said corresponding subsets of qubits having no common qubit (see page 3, col. 2Error-aware compilation is used to best select the appropriate subset and logical assignment of qubits on a device. For any circuit with a width less than the total number of qubits on the device, there is a combinatorially large range of logically equivalent circuits. Additional compilation passes select and rank the best implementations among these, accounting for device topology, tabulated gate errors, parallel-gate crosstalk, etc. This step is executed in runtime on user initiation of the pipeline (note: parallel quantum operations apply to logical qubits in the context of quantum circuits, and they are not limited on (any) physical qubits being used).
As per claim 13:
Pranav teaches that wherein no crosstalk is present between each of said corresponding subsets of qubits (see page 3, col. 1 In addition to errors impacting individual qubits, errors may also arise due to unwanted coherent coupling or semi-classical driving between nearby qubits, resulting in another substantive form of non-Markovian error;(note: : the limitation that "no crosstalk is present" is a system-level constraint rather than an implementation-specific feature, and crosstalk suppression techniques (e.g., dynamical decoupling, frequency detuning, optimal control pulses) are not limited to a specific technical implementation).
As per claim 14:
Pranav teaches that wherein each of said corresponding subsets of qubits is included in a corresponding hyperedge of an interaction hypergraph, wherein each of said corresponding hyperedges being unique for each of said corresponding subsets of qubits (see page 3, col. 1 These phenomena are known as crosstalk which may arise from a wide range of physical mechanisms. Quantum crosstalk emerges due to spurious coupling between qubits via the mechanism of device fabrication or operation. The most common spurious coupling in superconducting qubits is an unwanted ZZ coupling; in this process, a qubit acquires a deterministic phase shift that depends both on its state and a nearby qubit state)
As per claim 15:
Pranav teaches that a non-transient computer readable storage medium, storing computer instructions, wherein the computer instructions are used for causing a computer to execute the method according to claim 1 (see Fig. 1).
As per claim 16:
Pranav substantially teaches or discloses a system for characterizing implementation errors in a quantum logic operation g operating on a targeted set of qubits of a quantum processor, comprising a processor configured for executing computer-executable components stored in a memory, wherein the computer-executable components comprise (see abstract; see page 2, col. 1, Most hardware backends provide tabulated data for the error rate associated with each gate in an algorithm, as measured using device-level characterization protocols such as randomized benchmarking, cycle benchmarking and gateset tomography; and entire pipeline comprising error characterization as part of the error aware compilation and dynamical decoupling techniques, in order to characterize and mitigate errors, wherein said characterization is a result of said error-suppression protocol in Figure 1 , and page 3, col. 1 , last paragraph - page 4, col. 2, first paragraph ; and Fig. 1): (a) a sequence component, configured for generating at least one characterization sequence, said at least one characterization sequence including at least one refocusing sequence and said quantum logic operation (see abstract, dynamical decoupling sequences and its staggered variant to mitigate errors, said sequences amplifying and studying error effects such as coherent crosstalk (i.e., characterization sequences) "We introduce the key elements of this work ow, delivered as a software package called Fire Opal, and survey the underlying physical concepts: error-aware compilation, automated system-wide gate optimization, automated dynamical decoupling embedding for circuit-level error cancellation, and calibration- efficient measurement error mitigation.", page 16, col. 2, paragraph 2: "[...] to mitigate ZZ-error, the timings of bit ip on the two qubits need to be staggered and correlated.", page 16, col. 1 , last paragraph: "[...] crosstalk errors due to spurious ZZ coupling can be mitigated by a DD protocol.", wherein DD sequences, by definition suppress unwanted error terms (including crosstalk and idle errors), the at least one characterization sequence is configured for amplifying at least one target error parameter, and the at least one refocusing sequence is configured for reducing predefined crosstalk Pauli terms between said targeted set of qubits and another set of qubits of the quantum processor (see use of dynamical decoupling to mitigate errors such as ZZ crosstalk between qubits, as well as applying these sequences at the algorithmic level with knowledge of errors and device topology (i.e., refocusing sequences reducing predefined generator terms), in page 2, col. 2, paragraph 3, page 16, col. 1 , last paragraph, and page 15, col. 1 , first paragraph, second bullet); and (b) a characterization component, configured for characterizing errors in said quantum logic operation g, using said sequence (see page 2, col. 1, Most hardware backends provide tabulated data for the error rate associated with each gate in an algorithm, as measured using device-level characterization protocols such as randomized benchmarking, cycle benchmarking and gateset tomography; and entire pipeline comprising error characterization as part of the error aware compilation and dynamical decoupling techniques, in order to characterize and mitigate errors, wherein said characterization is a result of said error-suppression protocol in Figure 1 , and page 3, col. 1 , last paragraph - page 4, col. 2, first paragraph).
As per claim 17:
Pranav teaches that wherein said at least one target error parameter is a Pauli generator term P.sub.t, and wherein said at least one characterization sequence is configured for reducing predefined Pauli generator terms in said targeted set of qubits (seepage 16, col. 1 , last paragraph, Dynamical decoupling (DD) is an open-loop quantum control technique aimed at suppressing idling errors. In its simplest form, DD is implemented by periodic sequences of quantum bit flips, whose net effect is to approximately cancel unwanted couplings. Most traditional DD protocols are designed to reduce global dephasing (T2 processes), but different schemes exist for designing DD protocols for specific error-reducing tasks).
As per claim 18:
Pranav teaches that wherein said at least one refocusing sequence is any of: a dynamical decoupling sequence, and a twirling sequence (page 10, col. 2, paragraph 4, see Q-CTRL pipeline in Table Il, and Pauli twirling).
As per claim 19:
Pranav teaches that wherein said at least one refocusing sequence commutes with said Pauli generator term P.sub.t (seepage 16, col. 1 , last paragraph, Dynamical decoupling (DD) is an open-loop quantum control technique aimed at suppressing idling errors. In its simplest form, DD is implemented by periodic sequences of quantum bit flips, whose net effect is to approximately cancel unwanted couplings. Most traditional DD protocols are designed to reduce global dephasing (T2 processes), but different schemes exist for designing DD protocols for specific error-reducing tasks).
As per claim 20:
Pranav teaches that wherein a first refocusing sequence included in said at least one characterization sequence anti-commutes with a Pauli generator term of an ideal version of said quantum logic operation g corresponding said Pauli generator term P.sub.t (see page 10, col. 2, Statistical methods, such as zero-noise extrapolation, Pauli twirling and random compilation (see Appendix A) can follow our deterministic pipeline to further improve the accuracy of the expectation values by reducing the effect of Markovian errors at the price of extensive over head).
Allowable Subject Matter
9. Claims 7, 9, and 11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Dependent claim 10 is/are depend from allowable subject matter claim 9 and inherently include limitations therein and therefore are allowed as well.
Examiner Notes
10. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
11. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/ Examiner, Art Unit 2112