DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP-2022-054119, filed on 09/29/2022.
Information Disclosure Statement
The information disclosure statement (IDS) was received on 09/25/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Line 9 of claim 5 contains the phrase “first bear signals”. For examination purposes this will be interpreted as “first beat signals”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4, 10, 12-13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Reiher et. al (US 20230008816 A1), hereinafter Reiher, in view of Nayyar et al. (US 20160018511 A1), hereinafter Nayyar.
Regarding claim 1, Reiher discloses [Note – what is not clearly disclosed is strike-through]:
A radar apparatus, comprising:a first module (Reiher [0030] : “FIG. 2 shows the central evaluation unit 20”, further, Reiher Fig. 2, instance 12);
a second module (Reiher Fig. 2, instance 20, further Reiher [0030] “FIG. 2 shows the central evaluation unit 20 and two of the transmit/receive units 12 as separate blocks.”); and
the first module includes:a signal processing circuit which, in operation, outputs a plurality of beat signals respectively for a plurality of reception antennas (Reiher [0031] “These beat signals are evaluated for each receive antenna in a separate receive channel of the semiconductor module 22. In this case, the complex amplitudes of the beat signals are sampled and digitized at a high cycle rate over the duration of the measuring cycle. The digitized data form raw data, which are transferred to the central evaluation unit 20 via the raw data interface 14.”), and
a control circuit which, in operation, (Reiher Fig. 2, element 38, further, Reiher [0038] “The control unit 34 of the evaluation unit 20 and the control unit 38 of each transmit/receive unit 12 communicate with one another via one or more cores of the cable 18, which connects these components.”),
the second module includes:a detection circuit which, in operation, detects an object based on the plurality of beat signals received from the first module via the cable (Reiher [0032] “In the course of evaluation, the time signal is converted in each receive channel by fast Fourier transform into a spectrum in which each located object is distinguished as a peak at a specific frequency.”), and
a command circuit (Reiher [0032] “In the example shown, the central evaluation unit 20 is formed by a control device, which also controls the functions of the transmit/receive units and in which the time signals of all the transmit/receive units 12 are jointly evaluated in a fast processor 24 with associated working memory 26. ”).
Reiher fails to clearly disclose the limitation(s) below. Nayyar discloses:
a first module includes: a control circuit which, in operation, outputs a control command to the signal processing circuit in accordance with a start trigger command received from the second module via the cable, the control command being used for starting the signal processing circuit, and (Nayyar [0046] “For example, the processing unit 406 may use the SPI 528 to send control information, e.g., timing and frequencies of chirps, output power level, triggering of monitoring functions such as phase noise monitoring, etc., to the radar SOC 500.” Here the examiner notes that stop and start trigger commands are inherent to the operation of control circuits in master-slave radar configurations. )
the second module includes: a command circuit which, in operation, transmits the start trigger command to the first module (Nayyar [0035] “Further, the master radar SOC 402 is coupled to the slave radar SOC 404 to synchronize the operation of the slave radar SOC 404 with that of the master radar SOC 402.” Here the examiner notes that stop and start trigger commands are inherent to the operation of control circuits in master-slave radar configurations.)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Nayyar into the invention of Reiher. Both Reiher and Nayyar are considered analogous arts to the claimed invention as they both disclose modular FMCW radars for automotive applications. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the radar apparatus as disclosed by Reiher utilize a control circuit to output a control command in accordance to a start trigger to a signal processing circuit as taught by Nayyar. In general, it is obvious to those of ordinary skill I the art that a “control circuit” with synchronization capabilities would necessarily have a start and stop trigger to the signal processing units in the master / slave radars. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to modify the radar apparatus in order to synchronize the operations of master and slave radar units (See Nayyar [0035]).
Regarding claim 2, Reiher further discloses:
The radar apparatus according to claim 1, wherein:
the plurality of reception antennas include a plurality of first reception antennas and a plurality of second reception antennas (Reiher Fig. 2, Element 22 shows two sets of reception antennas. Furhter, Reiher [0033] “In the example shown, each transmit/receive unit 12 has a plurality of semiconductor modules 22, and each semiconductor module has its own raw data interface 14 with associated serializer 16. By way of example, it may be assumed that each semiconductor module 22 pre-evaluates and digitizes the receive signal from forty receive antennas Rx on parallel receive channels.” .);
the signal processing circuit includes a first signal processing circuit and a second signal processing circuit, the first signal processing circuit outputting first beat signals respectively for the plurality of first reception antennas, the second signal processing circuit outputting second beat signals respectively for the plurality of second reception antennas, the first beat signals being parallel to one another, the second beat signals being parallel to one another (Reiher [0033] “In the example shown, each transmit/receive unit 12 has a plurality of semiconductor modules 22, and each semiconductor module has its own raw data interface 14 with associated serializer 16. By way of example, it may be assumed that each semiconductor module 22 pre-evaluates and digitizes the receive signal from forty receive antennas Rx on parallel receive channels.”);
the first module includes a first conversion circuit and a second conversion circuit, the first conversion circuit converting the first beat signals being parallel to one another into first serial signals and outputting the first serial signals to the cable, the second conversion circuit converting the second beat signals being parallel to one another into second serial signals and outputting the second serial signals to the cable (Reiher [0031] “These beat signals are evaluated for each receive antenna in a separate receive channel of the semiconductor module 22. In this case, the complex amplitudes of the beat signals are sampled and digitized at a high cycle rate over the duration of the measuring cycle. The digitized data form raw data, which are transferred to the central evaluation unit 20 via the raw data interface 14.“); and
the second module includes a third conversion circuit that restores the first serial signals received via the cable into the first beat signals being parallel to one another, restores the second serial signals received via the cable into the second beat signals being parallel to one another, and outputs to the detection circuit the first beat signals restored and the second beat signals restored (Reiher [0034] “The central evaluation unit 20 has a deserializer 32 for each transmit/receive unit 12, with which the arriving signals are deserialized and then routed onward in parallel to the processor 24.”).
Regarding claim 4, Reiher further discloses:
The radar apparatus according to claim 2, wherein:
when receiving a stop command from the command circuit via the cable, the control circuit stops an operation of the first signal processing circuit and the second signal processing circuit within one frame (Reiher [0036] For control and synchronization functions, the central evaluation unit 20 contains a control unit 34, which receives a time signal from a local real-time clock 36.).
Those of ordinary skill in the art will recognize that a synchronized control circuits inherently issue start and stop commands instantaneously, which would be within one frame of the FMCW radar operation.
Regarding claim 10, Reiher in view of Nayyar discloses the radar apparatus according to claim 1. Reiher fails to disclose the limitation below. Nayyar discloses:
a reproduction circuit between the first module and the second module, the reproduction circuit shaping a waveform of a signal transmitted (Nayyar [0035] “Further, the master radar SOC 402 is coupled to the slave radar SOC 404 to synchronize the operation of the slave radar SOC 404 with that of the master radar SOC 402.” , further Nayar [0048] “Instead, the RFSYNTH 530 in the master radar SOC 402 provides the FMCW signals to be transmitted to the slave radar SOC 404 via the input buffer 536.”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Nayyar into the invention of Reiher. Both Reiher and Nayyar are considered analogous arts to the claimed invention as they both disclose modular FMCW radars for automotive applications. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the radar apparatus as disclosed by Reiher utilize a circuit to shape the transmitted signal of a slave radar according to a signal from the master radar as taught by Nayyar. Under the broadest reasonable interpretation of the phrase “a reproduction circuit” the RFSYNTH circuit of Nayyar modifies the operation of the slave radar to reproduce waveform properties of the master module, serving as a reproduction circuit. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to modify the radar apparatus of Reiher in order to transmit identical waveforms from both the master and slave radar units (See Nayyar [0035] and [0036]).
Regarding claim 12, Reiher discloses [Note: what is not clearly disclosed is strike-through]:
A radar signal processing method, comprising:transmitting a start trigger command from a command circuit of a second module to a control circuit of a first module via a cable connecting the first module to the second module (Reiher [0038] “The control unit 34 of the evaluation unit 20 and the control unit 38 of each transmit/receive unit 12 communicate with one another via one or more cores of the cable 18, which connects these components.”, further, Reiher [0032] “In the example shown, the central evaluation unit 20 is formed by a control device, which also controls the functions of the transmit/receive units and in which the time signals of all the transmit/receive units 12 are jointly evaluated in a fast processor 24 with associated working memory 26. ”).
receiving, by the control circuit of the first module, the start trigger command from the second module (Reiher [0039] “The local real-time clocks 36, 40 are adjusted relative to one another by occasional exchange of reference signals, such that the transmit/receive units 12 may optionally be synchronized with one another and their data coherently evaluated.”);
outputting, from the signal processing circuit started of the first module to a detection circuit of the second module, a plurality of beat signals respectively for a plurality of reception antennas connected to the signal processing circuit of the first module (Reiher [0005] “A succession of frequency ramps is transmitted within each measuring cycle. The radar echoes received in each receive channel are mixed with a component of the signal transmitted at the receive time, such that a lower frequency beat signal is obtained.”, further Reiher [0033] “By way of example, it may be assumed that each semiconductor module 22 pre-evaluates and digitizes the receive signal from forty receive antennas Rx on parallel receive channels. In the serializer 16, the time signals arriving in parallel in the forty channels are serialized and transferred one after the other to the central evaluation unit 20 as a serial signal on a single core of the cable 18. The cable 18 therefore does not need forty cores for each semiconductor module 22, but rather just one single core.”);
and detecting, by the detection circuit of the second module, an object based on the plurality of beat signals received from the first module via the cable (Reiher [0032] “In the course of evaluation, the time signal is converted in each receive channel by fast Fourier transform into a spectrum in which each located object is distinguished as a peak at a specific frequency.”).
Reiher fails to disclose the limitations below. Nayyar discloses:
outputting, in response to the start trigger command, a control command from the control circuit of the first module to a signal processing circuit of the first module, the control command being used for starting the signal processing circuit of the first module (Nayyar [0046] “For example, the processing unit 406 may use the SPI 528 to send control information, e.g., timing and frequencies of chirps, output power level, triggering of monitoring functions such as phase noise monitoring, etc., to the radar SOC 500.”, further Nayyar Fig. 4 reproduced below)
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It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Nayyar into the invention of Reiher. Both Reiher and Nayyar are considered analogous arts to the claimed invention as they both disclose modular FMCW radars for automotive applications. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the radar processing method as disclosed by Reiher to utilize a control circuit to output a control command in accordance to a start trigger to a signal processing circuit as taught by Nayyar. In general, it is obvious to those of ordinary skill I the art that a “control circuit” with synchronization capabilities would necessarily have a start and stop trigger to the signal processing units in the master / slave radars. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to modify the radar apparatus in order to synchronize the operations of master and slave radar units (See Nayyar [0035]).
Regarding claim 13, Reiher in view of Nayyar discloses the radar signal processing method according to claim 12. Reiher further discloses [Note: what is not clearly disclosed is strike-through]:
the plurality of beat signals include first beat signals being parallel to one another for a plurality of first reception antennas from among the plurality of reception antennas, and second beat signals being parallel to one another for a plurality of second reception antennas from among the plurality of reception antennas (Reiher [0033] “In the example shown, each transmit/receive unit 12 has a plurality of semiconductor modules 22, and each semiconductor module has its own raw data interface 14 with associated serializer 16. By way of example, it may be assumed that each semiconductor module 22 pre-evaluates and digitizes the receive signal from forty receive antennas Rx on parallel receive channels.”);
the first beat signals being parallel to one another are converted into first serial signals by a first conversion circuit of the first module and are output to the cable (Reiher [0031] “These beat signals are evaluated for each receive antenna in a separate receive channel of the semiconductor module 22. In this case, the complex amplitudes of the beat signals are sampled and digitized at a high cycle rate over the duration of the measuring cycle. The digitized data form raw data, which are transferred to the central evaluation unit 20 via the raw data interface 14.“);
the second beat signals being parallel to one another are converted into second serial signals by the first conversion circuit of the first module and are output to the cable (See above Reiher [0031] citation);
the first serial signals received via the cable are restored into the first beat signals being parallel to one another by a third conversion circuit of the second module (Reiher [0034] “The central evaluation unit 20 has a deserializer 32 for each transmit/receive unit 12, with which the arriving signals are deserialized and then routed onward in parallel to the processor 24.”);
the second serial signals received via the cable are restored into the second beat signals being parallel to one another by the third conversion circuit of the second module; and (See above Reiher [0034] citation)
the first beat signals restored and the second beat signals restored are output from the third conversion circuit to the detection circuit (Reiher Fig. 2, where the signal is transmitted from elements 32 to 24).
Regarding claim 15, Reiher in view of Nayyar discloses the radar signal processing method according to claim 12. Reiher further discloses:
additionally, when the control circuit of the first module receives a stop command from the command circuit of the second module via the cable, an operation of the signal processing circuit of the first module is stopped within one frame by the control circuit of the first module (Reiher [0036] For control and synchronization functions, the central evaluation unit 20 contains a control unit 34, which receives a time signal from a local real-time clock 36.).
Those of ordinary skill in the art will recognize that a synchronized control circuit inherently issues start / stop commands instantaneously, which would be within one frame of the FMCW radar operation.
Claim(s) 3, 5, 6-9, 14, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Reiher et. al (US 20230008816 A1), hereinafter Reiher, in view of Nayyar et al. (US 20160018511 A1), hereinafter Nayyar, and further in view of Rimini et al. (US 20210156954 A1), hereinafter Rimini.
Regarding claim 3, Reiher in view of Nayyar discloses the radar apparatus according to claim 1. Reiher further discloses [Note: what is not clearly disclosed is strike-through]:
the plurality of reception antennas include a plurality of first reception antennas and a plurality of second reception antennas (Reiher Fig. 2, Element 22 shows two sets of reception antennas.);
the signal processing circuit includes a first signal processing circuit and a second signal processing circuit, the first signal processing circuit outputting first beat signals respectively for the plurality of first reception antennas, the second signal processing circuit outputting second beat signals respectively for the plurality of second reception antennas, the first beat signals being parallel to one another, the second beat signals being parallel to one another (Reiher [0033] “In the example shown, each transmit/receive unit 12 has a plurality of semiconductor modules 22, and each semiconductor module has its own raw data interface 14 with associated serializer 16. By way of example, it may be assumed that each semiconductor module 22 pre-evaluates and digitizes the receive signal from forty receive antennas Rx on parallel receive channels.”);
the first module includes a first conversion circuit and a second conversion circuit, the first conversion circuit converting the first beat signals being parallel to one another into first serial signals and outputting the first serial signals to the cable, the second conversion circuit converting the second beat signals being parallel to one another into second serial signals and outputting the second serial signals to the cable; and (Reiher [0031] “These beat signals are evaluated for each receive antenna in a separate receive channel of the semiconductor module 22. In this case, the complex amplitudes of the beat signals are sampled and digitized at a high cycle rate over the duration of the measuring cycle. The digitized data form raw data, which are transferred to the central evaluation unit 20 via the raw data interface 14.“)
the second module includes a third conversion circuit that restores the first serial signals received via the cable into the first beat signals being parallel to one another, restores the second serial signals received via the cable into the second beat signals being parallel to one another, (Reiher [0034] “The central evaluation unit 20 has a deserializer 32 for each transmit/receive unit 12, with which the arriving signals are deserialized and then routed onward in parallel to the processor 24.”).
Reiher in view of Nayyar fails to disclose the limitation below. Rimini discloses:
and multiplexes in a time-division manner the first beat signals restored and the second beat signals restored (Rimini [0031] “A multiplexing circuit, which may be disposed within the radio-frequency integrated circuit, generates at least one composite radar beat signal by multiplexing the radar beat signals together. The multiplexing circuit may use, for example, analog frequency-division multiplexing (FDM), digital frequency-division multiplexing, code-division multiplexing (CDM), digital time-division multiplexing (TDM), or digital bit packing.”)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the apparatus as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini. Nayyar does mention the use of a multiplexor, but not in the context of the processing of beat signals (See Nayyar [0049]). One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexing method to transmit the second beat signals restored in a composite signal, reducing the overall number of inputs to the object detecting processor (See Rimini [0004-0005]).
Regarding claim 5, Reiher in view of Nayyar discloses the apparatus according to claim 2. Reiher further discloses [Note: what is not clearly disclosed is strike-through]:
the first module comprises a plurality of the first modules, and the third conversion circuit comprises a plurality of the third conversion circuits; and (Reiher Fig. 1, Element 12, Fig. 2 Element 42.)
the plurality of third conversion circuits are provided to correspond respectively to the plurality of first modules (Reiher [0038] “The control unit 34 of the evaluation unit 20 and the control unit 38 of each transmit/receive unit 12 communicate with one another via one or more cores of the cable 18, which connects these components. In the example shown, each control unit is associated with a serializer/deserializer 42,”),
wherein each of the plurality of third conversion circuits which, in operation, restores serial signals output from a corresponding first module into first beat signals being parallel to one another and second beat signals being parallel to one another, (Reiher [0034] “The central evaluation unit 20 has a deserializer 32 for each transmit/receive unit 12, with which the arriving signals are deserialized and then routed onward in parallel to the processor 24.”).
Reiher in view of Nayyar fails to disclose the limitation below. Rimini discloses:
and multiplexes in a time-division manner the first bear signals restored and the second beat signals restored (Rimini [0031] “A multiplexing circuit, which may be disposed within the radio-frequency integrated circuit, generates at least one composite radar beat signal by multiplexing the radar beat signals together. The multiplexing circuit may use, for example, analog frequency-division multiplexing (FDM), digital frequency-division multiplexing, code-division multiplexing (CDM), digital time-division multiplexing (TDM), or digital bit packing.”)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the apparatus as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini. Nayyar does mention the use of a multiplexor, but not in the context of the processing of beat signals (See Nayyar [0049]). One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexing method to transmit the second beat signals restored in a composite signal, reducing the overall number of inputs to the object detecting processor (See Rimini [0004-0005]).
Regarding claim 6, Reiher in view of Nayyar discloses the radar apparatus of claim 1. Reiher in view of Nayyar further discloses [ Note: what is not clearly disclosed is strike-through]:
the plurality of reception antennas include a plurality of first reception antennas and a plurality of second reception antennas (Reiher Fig. 2, Element 22 shows two sets of reception antennas.);
the signal processing circuit includes a first signal processing circuit that outputs first beat signal respectively for the plurality of first reception antennas in parallel, and a second signal processing circuit that outputs a second beat signal respectively for the plurality of second reception antennas in parallel (Nayar Fig. 4, further, Nayar [0035] “The master radar SOC 402 and the slave radar SOC 404 each have the architecture of the example FMCW radar SOC of FIG. 5.”);
the first module includes a first conversion circuit that converts the first beat signals being parallel to one another into first serial signals, converts the second beat signals being parallel to one another into second serial signals (Reiher [0031] “These beat signals are evaluated for each receive antenna in a separate receive channel of the semiconductor module 22. In this case, the complex amplitudes of the beat signals are sampled and digitized at a high cycle rate over the duration of the measuring cycle. The digitized data form raw data, which are transferred to the central evaluation unit 20 via the raw data interface 14.“
the second module includes a second conversion circuit that restores the first serial signals received via the cable into the first beat signals being parallel to one another, restores the second serial signals received via the cable into the second beat signals being parallel to one another, and (Reiher [0034] “The central evaluation unit 20 has a deserializer 32 for each transmit/receive unit 12, with which the arriving signals are deserialized and then routed onward in parallel to the processor 24.”)
Reiher in view of Nayyar fails to the multiplexing of signals. Rimini discloses the multiplexing of radar beat signals (Rimini [0031] “A multiplexing circuit, which may be disposed within the radio-frequency integrated circuit, generates at least one composite radar beat signal by multiplexing the radar beat signals together. The multiplexing circuit may use, for example, analog frequency-division multiplexing (FDM), digital frequency-division multiplexing, code-division multiplexing (CDM), digital time-division multiplexing (TDM), or digital bit packing.”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the apparatus as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini. This is applicable to data transfer both in the cable between the two modules and to transmit a composite of the first and second signals to a detection circuit. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexing method to transmit the second beat signals restored in a composite signal, reducing the overall number of inputs to the object detecting processor (See Rimini [0004-0005]). One also would have been motivated to perform multiplexing before transmission through the cable in order to reduce the number of required transmission channels (See Rimini [0005]).
Regarding claim 7, Reiher in view of Nayyar, and further in view of Rimini discloses the radar apparatus according to claim 6. Reiher further teaches [Note: what is not clearly disclosed is strike-through]:
the first module (Reiher Fig. 2); and
the second module Reiher Fig. 2).
Reiher in view of Nayyar fails to teach the limitations below. Rimini teaches:
includes a compression circuit that compresses (Rimini Fig. 4, further, Rimini [0046] “In general, the multiplexing circuit 130 combines respective receive signals that propagate through the multiple receive chains into one or more composite signals. ”)
includes an expansion circuit that expands (Rimini [0049] “In FIG. 1, the processor 126 includes a demultiplexing circuit 132 and a digital beamformer 134. The demultiplexing circuit 132 demultiplexes the composite radar beat signal to extract the radar beat signals.”)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the apparatus as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini in the context of a compression circuit. In the broadest reasonable interpretation, one could interpret both serialization and multiplexing as a form of compression. The multiplexing of signals reduces the required number of wires and contacts necessary for signal transmission between radar and processing modules. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexor to combine (compress) the antenna array signals, then perform the inversion separate (decompress) said signals before processing. One also would have been motivated to perform multiplexing before transmission through the cable in order to reduce the number of required transmission channels (See Rimini [0005]).
Regarding claim 8, Reiher in view of Nayyar, further in view of Rimini, teaches the radar apparatus according to claim 7. Reiher further teaches [Note – what is not clearly disclosed is strike-through]:
the first module comprises a plurality of the first modules; and (Reiher, Fig. 1 element(s) 12, further, Fig. 2 element(s) 12)
beat signals being parallel to one another from a first module different from the first module
Reiher in view of Nayyar fail to teach the limitation below. Rimini teaches:
are input to the compression circuit (Rimini [0046] “In general, the multiplexing circuit 130 combines respective receive signals that propagate through the multiple receive chains into one or more composite signals. ”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the apparatus as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini in the context of a compression circuit. In the broadest reasonable interpretation, one could interpret both serialization and multiplexing as a form of compression. The multiplexing of signals reduces the required number of wires and contacts necessary for signal transmission between radar and processing modules. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexor to combine (compress) the antenna array signals, then perform the inversion separate (decompress) said signals before processing. One also would have been motivated to perform multiplexing before transmission through the cable in order to reduce the number of required transmission channels (See Rimini [0005]).
Regarding claim 9, Reiher in view of Nayyar, further in view of Rimini discloses the radar apparatus of claim 6. Nayyar further discloses:
a third conversion circuit that converts a serial signal output from a module different from the first module into a parallel beat signal and outputs the parallel beat signal to the first conversion circuit of the first module (Nayyar [0035] “Further, the master radar SOC 402 is coupled to the slave radar SOC 404 to synchronize the operation of the slave radar SOC 404 with that of the master radar SOC 402.”, further, Nayyar [0036] “The processing unit 406 is coupled to the master radar SOC 402 and the slave radar SOC 404 via a serial interface to receive data from the radar SOCs. ”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the radar apparatus as disclosed by Reiher to convert a serial output from one module to a beat signal, then use it as an input to a first conversion circuit as taught by Nayyar. Relationships between what are known as “master” and “slave” radars are well-known within the art. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize serialization and deserialization conversion circuits in order to transmit signals between codependent radar modules in order to synchronize their beat signal generation. Reiher has previously established that the serialization of data is beneficial to transmit data streams over extended distances, over which data transfer resources may be slim (See Reiher [0015]).
Regarding claim 14, Reiher in view of Nayyar the radar processing method of claim 13. Reiher in view of Nayyar fails to teach the limitation below. Rimini discloses:
the first beat signals restored and the second beat signals restored are further multiplexed in a time-division manner and output from the third conversion circuit to the detection circuit (Rimini [0031] “A multiplexing circuit, which may be disposed within the radio-frequency integrated circuit, generates at least one composite radar beat signal by multiplexing the radar beat signals together. The multiplexing circuit may use, for example, analog frequency-division multiplexing (FDM), digital frequency-division multiplexing, code-division multiplexing (CDM), digital time-division multiplexing (TDM), or digital bit packing.”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the method as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini. Nayyar does mention the use of a multiplexor, but not in the context of the processing of beat signals (See Nayyar [0049]). One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexing method to transmit the second beat signals restored in a composite signal, reducing the overall number of inputs to the object detecting processor (See Rimini [0004-0005], Reiher [0015]).
Regarding claim 16, Reiher in view of Nayyar discloses the radar processing signal according to claim 13. Reiher further discloses:
the first module comprises a plurality of the first modules, and the third conversion circuit comprises a plurality of the third conversion circuits (Reiher Fig. 1, Element 12, Fig. 2 Element 42.);
the plurality of third conversion circuits are provided to correspond respectively to the plurality of first modules (Reiher [0038] “The control unit 34 of the evaluation unit 20 and the control unit 38 of each transmit/receive unit 12 communicate with one another via one or more cores of the cable 18, which connects these components. In the example shown, each control unit is associated with a serializer/deserializer 42,”);
serial signals output from each of the plurality of first modules are restored by a corresponding one of the plurality of third conversion circuits into first beat signals being parallel to one another and second beat signals being parallel to one another; and (Reiher [0034] “The central evaluation unit 20 has a deserializer 32 for each transmit/receive unit 12, with which the arriving signals are deserialized and then routed onward in parallel to the processor 24.”)
the first beat signals restored and the second beat signals restored are
Reiher in view of Nayyar fails to disclose the limitation below. Rimini discloses:
multiplexed in a time-division manner by each of the plurality of third conversion circuits and output to the detection circuit (Rimini [0031] “A multiplexing circuit, which may be disposed within the radio-frequency integrated circuit, generates at least one composite radar beat signal by multiplexing the radar beat signals together. The multiplexing circuit may use, for example, analog frequency-division multiplexing (FDM), digital frequency-division multiplexing, code-division multiplexing (CDM), digital time-division multiplexing (TDM), or digital bit packing.”)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the apparatus as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini. Nayyar does mention the use of a multiplexor, but not in the context of the processing of beat signals (See Nayyar [0049]). One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexing method to transmit the second beat signals restored in a composite signal, reducing the overall number of inputs to the object detecting processor (See Rimini [0004-0005]).
Regarding claim 17, Reiher in view of Nayyar, and further in view of Rimini, teaches the radar signal processing method of claim 14. Reiher further teaches:
additionally, the first serial signals and the second serial signals are (Reiher Fig. 2, further Reiher [0031] “These beat signals are evaluated for each receive antenna in a separate receive channel of the semiconductor module 22. In this case, the complex amplitudes of the beat signals are sampled and digitized at a high cycle rate over the duration of the measuring cycle. The digitized data form raw data, which are transferred to the central evaluation unit 20 via the raw data interface 14.“).
Reiher fails to teach the use of time-division multiplexing. Rimini teaches:
multiplexed in a time-division manner
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the apparatus as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini. Nayyar does mention the use of a multiplexor, but not in the context of the processing of beat signals (See Nayyar [0049]). One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexing method to transmit the second beat signals restored in a composite signal, improving the transmission capacity of the cable (See Rimini [0004-0005]).
Regarding claim 18,
additionally, the first beat signals being parallel to one another and the second beat signals being parallel to one another (Reiher Fig. 2)
the first beat signals being parallel to one another and the second beat signals being parallel to one another Reiher Fig. 2)
Reiher in view of Nayyar fails to teach the limitations below. Rimini teaches:
includes a compression circuit that compresses (Rimini Fig. 4, further, Rimini [0046] “In general, the multiplexing circuit 130 combines respective receive signals that propagate through the multiple receive chains into one or more composite signals. ”)
includes an expansion circuit that expands (Rimini [0049] “In FIG. 1, the processor 126 includes a demultiplexing circuit 132 and a digital beamformer 134. The demultiplexing circuit 132 demultiplexes the composite radar beat signal to extract the radar beat signals.”)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the process as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini in the context of a compression circuit. In the broadest reasonable interpretation, one could interpret both serialization and multiplexing as a form of compression. The multiplexing of signals reduces the required number of wires and contacts necessary for signal transmission between radar and processing modules. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexor to combine (compress) the antenna array signals, then perform the inversion separate (decompress) said signals before processing. One also would have been motivated to perform multiplexing before transmission through the cable in order to reduce the number of required transmission channels (See Rimini [0005]).
Regarding claim 19, Reiher in view of Nayyar, further in view of Rimini, teaches the radar apparatus according to claim 18. Reiher further teaches [Note – what is not clearly disclosed is strike-through]:
the first module comprises a plurality of the first modules; and (Reiher, Fig. 1 element(s) 12, further, Fig. 2 element(s) 12)
a parallel beat signal from a different first module is input to
Reiher in view of Nayyar fail to teach the limitation below. Rimini teaches:
is input to the compression circuit of (Rimini [0046] “In general, the multiplexing circuit 130 combines respective receive signals that propagate through the multiple receive chains into one or more composite signals. ”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Rimini into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Rimini are considered analogous arts to the claimed invention as all disclose methods for radar sensing by synthesizing the signals of multiple FMCW radar units. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the process as disclosed by Reiher in view of Nayyar to utilize multiplexing methods as taught by Rimini in the context of a compression circuit. In the broadest reasonable interpretation, one could interpret both serialization and multiplexing as a form of compression. The multiplexing of signals reduces the required number of wires and contacts necessary for signal transmission between radar and processing modules. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to utilize a multiplexor to combine (compress) the antenna array signals, then perform the inversion separate (decompress) said signals before processing. One also would have been motivated to perform multiplexing before transmission through the cable in order to reduce the number of required transmission channels (See Rimini [0005]).
Regarding claim 20, Reiher in view of Nayyar, and further in view of Rimini discloses the radar signal processing method according to claim 18. Nayyar further discloses:
the first module comprises a plurality of the first modules (Reiher, Fig. 1 element(s) 12, further, Fig. 2 element(s) 12)
serial signals output from a first module different from the first module are converted by the third conversion circuit of the second module into the beat signals being parallel to one another, and are output to the first conversion circuit of the first module (Nayyar [0035] “Further, the master radar SOC 402 is coupled to the slave radar SOC 404 to synchronize the operation of the slave radar SOC 404 with that of the master radar SOC 402.”, further, Nayyar [0036] “The processing unit 406 is coupled to the master radar SOC 402 and the slave radar SOC 404 via a serial interface to receive data from the radar SOCs. ”).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Reiher et. al (US 20230008816 A1), hereinafter Reiher, in view of Nayyar et al. (US 20160018511 A1), hereinafter Nayyar, and further in view of Bauer et al. (US 20210263147 A1), hereinafter Bauer.
Regarding claim 11, Reiher in view of Nayyar discloses the radar apparatus according to claim 1. Reiher in view of Nayyar fails to disclose the limitation below. Bauer discloses:
the detection circuit detects a fault in the signal processing circuit based on the plurality of beat signals (Bauer [0130] The signal received by receiver RXA is then correlated with the signal received by receiver RXB (step 362). If the correlation results exceed a threshold, i.e. the two received signals match sufficiently (step 364), then both receivers RXA and RXB are declared operational and no fault is detected (step 365).).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features as disclosed by Bauer into the invention of Reiher in view of Nayyar. The set of Reiher, Nayyar, and Bauer are considered analogous arts to the claimed invention as they disclose systems for processing beat signals in FMCW radars. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the process as disclosed by Reiher in view of Nayyar to utilize fault detection based on the processing of the beat signals as taught by Bauer. One of ordinary skill in the art prior to the effective filing date of the claimed invention would have been motivated to modify the process to include fault detection in order to provide redundancy amongst modules in the event that one fails (See Bauer [0013]), where in the context of automobile a malfunctioning radar system would pose a serious safety risk.
Conclusion
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/T.J.H./Examiner, Art Unit 3648
/RESHA DESAI/Supervisory Patent Examiner, Art Unit 3648
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