Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 09/25/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 5 is objected to because of the following informalities: Regarding claim 5, in line 8-9, “the first connection surface (400) of the first DC voltage terminal element (44)” appears that it should read as “the first connection surface (400) of the first DC voltage terminal element (40)”, since reference numeral (44) designates the third DC voltage terminal element rather than the first. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 3, 4, 7, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2019/0238062 A1, hereinafter “Lu”) in view of Hattori (JP 6338543 B2, hereinafter “Hattori”). Regarding claim 1, Lu discloses (see Figs. 6 and 7) a three-level power semiconductor module (3-level T-type NPC inverter/rectifier module of Fig. 7) comprising: a switching device (the three-phase T-type NPC inverter circuit shown in Fig. 7) with a first DC voltage terminal element (+VBUS/2 terminal of Fig. 7), a second DC voltage terminal element (-VBUS/2 terminal of Fig. 7), and a third DC voltage terminal element (the midpoint node between the VBUS/2 capacitors corresponding to 0 Vdc neutral, see Fig. 7) which form a group of DC voltage terminals; an AC voltage terminal element (output terminals connecting to the load shown in Fig. 7); the switching device has a normal direction and is formed as a TNPC circuit arrangement (see [0053] "FIG. 6 shows a schematic block diagram representing one phase leg of a 3-level T-type NPC inverter topology"), which has a DC branch with an upper first switch (high side switch HSS/S1 of Fig. 6) whose power input is connected to a high potential (+Vdc) of a DC voltage source (see [0053] "the outer switches, comprising a high side switch (HSS) S1 and low side switch (LSS) S4, are connected in a half bridge configuration between the DC link terminals, +Vdc and −Vdc"); a lower fourth switch (low side switch LSS/S4 of Fig. 6) whose power output is connected to a low potential (-Vdc) of a DC voltage source and with a center tap (output node N to Vac of Fig. 6); and a T branch with a second switch (middle path switch S2 of Fig. 6) whose power input is connected indirectly or directly to intermediate potential (0 Vdc neutral; see [0053] "A neutral clamping leg comprising middle path switches S2 and S3 is connected between the neutral link terminal, 0 Vdc, and the output node N") and with a third switch (middle path switch S3 of Fig. 6) connected in series with the second switch (S2), whose power input is connected indirectly or directly to the center tap.
Lu does not disclose wherein the first switch is formed of a plurality of first part switches; wherein a majority of the part switches lie in a direction from the group of DC voltage terminals to the AC voltage terminal on a first straight line; wherein the fourth switch is formed of a plurality of fourth part switches; and wherein a majority of the fourth part switches lie in a direction from the group of DC voltage terminals to the AC voltage terminal on a second straight line adjacent to the first and a focal point of the second and third switch lying in the direction from the group of DC voltage terminals to the AC voltage terminal on a third straight line.
However, Hattori teaches (see Figs. 4 and 5) a three-level power semiconductor module (power module unit 110) wherein a first switch (first switching element 1) is formed of a plurality of first part switches (see [0064] "first switching element group includes two or more first switching elements 1 connected in parallel"), wherein a majority of the first part switches lie on a first straight line (L1) in a direction from a group of DC voltage terminals (positive terminal P, neutral terminal C, negative terminal N) to an AC voltage terminal (AC) (see [0046] "the first collector terminal 1a of the first switching element 1 and the second emitter terminal 2b of the second switching element 2 are arranged on the first straight line L1"); a fourth switch (fourth switching element 4) is formed of a plurality of fourth part switches (see [0065] "two or more third switching elements 3 connected in parallel and two or more fourth switching elements 4 connected in parallel"), wherein a majority of the fourth part switches lie on a second straight line (L2) adjacent to the first (see [0049] "the third collector terminal 3a of the third switching element 3 and the fourth emitter terminal 4b of the fourth switching element 4 are arranged on a second straight line L2 parallel to the first straight line L1"); and a focal point of neutral clamping elements (first diode element 5 and second diode element 6, occupying the position of the second and third switches in the combination) lies on a third straight line (L3) in the direction from the DC voltage terminals to the AC voltage terminal (see [0054] "the first anode terminal 5a and the first cathode terminal 5b of the first diode element 5 are arranged on a third straight line L3 parallel to the first straight line L1 and adjacent thereto").
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the three-level power semiconductor module of Lu wherein the first switch is formed of a plurality of first part switches arranged on a first straight line, the fourth switch is formed of a plurality of fourth part switches arranged on a second straight line adjacent to the first, and a focal point of the second and third switch lies on a third straight line, as taught by Hattori, because it can help reduce the parasitic inductance of the wiring connecting the power semiconductor elements and thereby suppress surge voltage (see [0006]-[0007] of Hattori "reducing the parasitic inductance of the wiring connecting the power semiconductor elements to each other ... thereby suppressing the surge voltage"), while also enabling higher current-handling capability through the parallel connection of part switches.
Regarding claim 2, Lu discloses (see Figs. 6 and 7) wherein the current-carrying capacity of the first and fourth switch (S1, S4) is identical to and greater than that of the second and third switch (S2, S3), respectively (see Fig. 6 of Lu, which annotates the outer high side and low side switches S1 and S4 as "Power switches (2Vdc) with higher current rating e.g. 1200V/100A" and the middle path switches S2 and S3 as "Power switches (Vdc) with lower current rating e.g. 600V/60A"; see also [0053] "S2 and S3 may be implemented with smaller, lower cost devices ... they may be rated for lower current than S1 and S4").
Regarding claim 3, Lu does not disclose wherein the third straight line makes an angle of 0° with the first and second straight line, in each case. However, Hattori teaches (see Figs. 4 and 5) wherein the third straight line (L3) makes an angle of 0° with the first and second straight line (L1, L2), in each case (see [0054] of Hattori "third straight line L3 parallel to the first straight line L1 and adjacent thereto"; see also [0056] "the second anode terminal 6a and the second cathode terminal 6b of the second diode element 6 are arranged on a fourth straight line L4 parallel to the second straight line L2 and adjacent thereto"; Examiner's Note: an angle of 0° satisfies the claimed limitation of less than 45°). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the three-level power semiconductor module of Lu wherein the third straight line makes an angle of 0° with the first and second straight line, in each case, as taught by Hattori, because it can help reduce the parasitic inductance of the wiring connecting the power semiconductor elements and thereby suppress surge voltage (see [0006]-[0007] of Hattori "reducing the parasitic inductance of the wiring connecting the power semiconductor elements to each other ... thereby suppressing the surge voltage").
Regarding claim 4, Lu discloses (see Figs. 6 and 7) wherein the respective switch (S1, S2, S3, S4) is formed as a power semiconductor component, and the respective power semiconductor component is formed as one of an IGBT, an IGBT with antiparallel-connected diodes, a MOS-FET, a SiC-MOS-FET, a HEMT, and a GaN-HEMT (see [0026] of Lu "the high side and low side outer switches, S1 and S4, of the 3-level T-type NPC inverter comprise Si IGBTs and diodes, and the middle switches, S2 and S3, of the neutral clamping leg comprise GaN HEMTs"; see also [0009] "SiC MOSFETs"; see further [0027] "the anti-parallel diodes of Si IGBT switches S1 and S4 comprise faster SiC Schottky barrier diodes instead of Si diodes").
Regarding claim 7, Lu discloses (see Figs. 6 and 7) wherein the first DC voltage terminal element is connected to the high potential (DCP), the second DC voltage terminal element is connected to the low potential (DCM), and the third DC voltage terminal element is connected to the intermediate potential (DCN) (see Fig. 7 of Lu, where the upper capacitor terminal +VBUS/2 corresponds to the high potential DCP, the lower capacitor terminal -VBUS/2 corresponds to the low potential DCM, and the midpoint node 0 Vdc between the two capacitors corresponds to the intermediate potential DCN; see also [0053]).
Regarding claim 11, Lu does not disclose wherein all the DC voltage terminal elements are arranged on a first narrow side of the housing. However, Hattori teaches (see Figs. 4 and 5) wherein all the DC voltage terminal elements are arranged on a first narrow side of the housing (see Fig. 4 of Hattori, where positive terminal P, neutral terminal C, and negative terminal N are all arranged on a first narrow side of the power module unit 110). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the three-level power semiconductor module of Lu wherein all the DC voltage terminal elements are arranged on a first narrow side of the housing, as taught by Hattori, because it can help reduce the parasitic inductance of the wiring connecting the power semiconductor elements and thereby suppress surge voltage (see [0006]-[0007] of Hattori "reducing the parasitic inductance of the wiring connecting the power semiconductor elements to each other ... thereby suppressing the surge voltage"), by keeping the DC terminals close in proximity.
Regarding claim 12, Lu does not disclose wherein the AC voltage terminal element is arranged on a second narrow side of the housing. However, Hattori further teaches (see Figs. 4 and 5) wherein the AC voltage terminal element is arranged on a second narrow side of the housing (see Fig. 4 of Hattori, where the AC terminal 34 is arranged on a second narrow side of the power module unit 110 opposite the side on which the DC voltage terminals P, C, N are arranged). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the three-level power semiconductor module of Lu wherein the AC voltage terminal element is arranged on a second narrow side of the housing, as taught by Hattori, because it can help reduce the parasitic inductance of the wiring connecting the power semiconductor elements and thereby suppress surge voltage (see [0006]-[0007] of Hattori "reducing the parasitic inductance of the wiring connecting the power semiconductor elements to each other ... thereby suppressing the surge voltage"), by keeping the AC terminal opposite to the DC terminals.
Claims 5, 6, 8, 9, 10, 13, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Hattori, further in view of Kobolla et al. (US 2019/0020285 A1, hereinafter “Kobolla”). Regarding claim 5, Lu does not disclose wherein the respective connection surfaces of the respective DC voltage terminal elements each have an identical normal direction, and are arranged next to one another in projection in the normal direction; wherein the third connection surface of the third DC voltage terminal element lies in a first plane; and the first connection surface of the first DC voltage terminal element lies in a second plane parallel to the first when viewed in the normal direction.
However, Kobolla teaches (see Figs. 1, 6, and 7) a power electronics submodule wherein DC voltage terminal elements (first DC voltage terminal element 50, second DC voltage terminal element 52) have connection surfaces with an identical normal direction (see [0037] "the respective contact regions of the DC voltage terminal elements 50, 52 lie on the respective side which is averted from the cooling device 3"), and wherein the second DC voltage terminal element lies in a first plane while the first DC voltage terminal element lies in a second plane parallel to the first in the normal direction with an insulating device disposed therebetween (see [0041]-[0042] "the second DC voltage terminal element 52 is set back in relation to the first ... the insulating device 54 is arranged in a planar fashion between the DC voltage terminal elements").
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the three-level power semiconductor module of Lu as modified by Hattori wherein the respective connection surfaces of the respective DC voltage terminal elements each have an identical normal direction and are arranged next to one another in projection, wherein the third connection surface lies in a first plane and the first connection surface lies in a second plane parallel to the first, as taught by Kobolla, because it can help achieve a low-inductance and compact terminal arrangement that simplifies the busbar connection to the DC link capacitor while providing electrical insulation between adjacent DC potentials (see [0010] and [0037] of Kobolla).
Regarding claim 6, Lu does not disclose wherein the second connection surface of the second DC voltage terminal element lies in the second plane when viewed in the normal direction. However, Kobolla teaches (see Figs. 1, 6, and 7) wherein the second connection surface of the second DC voltage terminal element lies in the second plane when viewed in the normal direction (see Fig. 6 and [0042] of Kobolla, where the contact region of the second DC voltage terminal element 52 is arranged in the same plane as the contact region of the first DC voltage terminal element 50 when viewed in the normal direction averted from the cooling device). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the three-level power semiconductor module of Lu as modified by Hattori wherein the second connection surface of the second DC voltage terminal element lies in the second plane when viewed in the normal direction, as taught by Kobolla, because it can help achieve a low-inductance and compact terminal arrangement that simplifies the busbar connection to the DC link capacitor while providing electrical insulation between adjacent DC potentials (see [0010] and [0037] of Kobolla).
Regarding claim 8, Lu does not disclose wherein all the connection surfaces lie next to one another, in a projection in the normal direction, and not in series. However, Kobolla teaches (see Figs. 1, 6, and 7) wherein all the connection surfaces lie next to one another, in a projection in the normal direction, and not in series (see Fig. 4 of Hattori, where the connection surfaces of P, C, and N lie next to one another along the narrow side of the housing in a projection in the normal direction; see further [0037] and [0041] of Kobolla "the respective contact regions of the DC voltage terminal elements 50, 52 lie on the respective side which is averted from the cooling device 3"). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the three-level power semiconductor module of Lu as modified by Hattori wherein all the connection surfaces lie next to one another, in a projection in the normal direction, and not in series, as taught by Kobolla, because it can help achieve a low-inductance and compact terminal arrangement that simplifies the busbar connection to the DC link capacitor while providing electrical insulation between adjacent DC potentials (see [0010] and [0037] of Kobolla).
Regarding claim 9, Lu does not disclose wherein a first line section of the first DC voltage terminal element, directly connected to the first connection surface, aligns at least in sections with a connection surface of an adjacent DC voltage terminal element in the normal direction. However, Kobolla teaches (see Figs. 1, 6, and 7) wherein a first line section of the first DC voltage terminal element, directly connected to the first connection surface, aligns at least in sections with a connection surface of an adjacent DC voltage terminal element in the normal direction (see Fig. 6 and [0058]-[0059] of Kobolla "the first DC voltage terminal element 50 extends with its main extent above the second DC voltage terminal element 52 in the normal direction"; the first DC voltage terminal element 50 has a line section directly adjoining its contact region that aligns laterally with the contact region of the second DC voltage terminal element 52 in the normal direction). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the three-level power semiconductor module of Lu as modified by Hattori wherein a first line section of the first DC voltage terminal element, directly connected to the first connection surface, aligns at least in sections with a connection surface of an adjacent DC voltage terminal element in the normal direction, as taught by Kobolla, because it can help achieve a low-inductance and compact terminal arrangement that simplifies the busbar connection to the DC link capacitor while providing electrical insulation between adjacent DC potentials (see [0010] and [0037] of Kobolla).
Regarding claim 10, Lu does not disclose a second line section of the second DC voltage terminal element, directly connected to the second connection surface, aligns at least in sections with the third connection surface of the third DC voltage terminal element in the normal direction. However, Kobolla teaches (see Figs. 1, 6, and 7) wherein a second line section of the second DC voltage terminal element, directly connected to the second connection surface, aligns at least in sections with the third connection surface of the third DC voltage terminal element in the normal direction (the corresponding line-section alignment for the second DC voltage terminal element - see Fig. 6 and [0058]-[0059] of Kobolla, where the same stacking principle disclosed for the first DC voltage terminal element 50 in alignment with the second DC voltage terminal element 52 is applied symmetrically). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the three-level power semiconductor module of Lu as modified by Hattori wherein a second line section of the second DC voltage terminal element, directly connected to the second connection surface, aligns at least in sections with the third connection surface of the third DC voltage terminal element in the normal direction, as taught by Kobolla, because it can help achieve a low-inductance and compact terminal arrangement that simplifies the busbar connection to the DC link capacitor while providing electrical insulation between adjacent DC potentials (see [0010] and [0037] of Kobolla). Regarding claim 13, Lu does not disclose wherein a centrally arranged fastening cut-out extends through the switching device. However, Kobolla teaches (see Figs. 1, 6, and 7) a power electronics submodule (2) having a switching device (4) and an arrangement on a support device (3) configured as a cooling device, wherein a centrally arranged fastening cut-out extends through the switching device area (see 92 of Fig. 6, a pressure loading device incorporating a central bolt screwed to the cooling device and applying pressure via a disc spring to a pressure device 28 arranged above the switching device, and Fig. 7 description further teaches that the recess 500 of the first DC voltage terminal element, the recess 52) of the second DC voltage terminal element, the geometrical mid-point 400 of the switching device 4, and the recess 560 of the AC voltage terminal element are arranged on a single dash-dotted line passing through the geometric mid-point of the switching device, such that the central pressure loading device exerts pressure on the pressure device in a normal direction perpendicular to the substrate, in alignment with the geometric mid-point 400 of the switching device; see also claim 8 of Kobolla, reciting that “the first recess in the first supporting body, a geometrical midpoint of the switching device, and the second recess in the second supporting body are arranged in a single line”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the three-level power semiconductor module of Lu as modified by Hattori to include a centrally arranged fastening cut-out extending through the switching device, as taught by Kobolla, because doing so provides a single, centrally located mounting and pressure-introduction point uniformly aligned with the geometrical mid-point of the switching device, which enables a thermally-conductive connection between the submodule and the cooling device while providing low-inductance electrical connection to the DC and AC voltage connecting elements. Regarding claim 14, the combination of Lu and Hattori teaches each three-level power semiconductor module as set forth above with respect to claim 1 (see rejection of Claim 1 above).
Lu further teaches a power electronic arrangement comprising a plurality of phase legs (three phase legs in Fig. 7 of Lu, each of which is a three-level T-type NPC inverter/rectifier unit) arranged side by side to form a three-phase inverter/rectifier system (see [0057] of Lu "a three-phase hybrid 3-level T-type NPC inverter/rectifier implemented as a hybrid inverter/rectifier module"). Lu does not disclose arranging a plurality of power semiconductor submodules in a common arrangement with their longitudinal sides next to one another in a row.
However, Kobolla teaches (see Figs. 1, 6, and 7) arranging a plurality of power semiconductor submodules in a common arrangement with their longitudinal sides next to one another in a row (see [0020] of Kobolla "a plurality of submodules, having a common overall housing, constitute a power module"), wherein the DC voltage terminal elements of the plurality of submodules are also arranged in a row to facilitate connection to common DC voltage busbars (see Figs. 1 and 6 of Kobolla).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange a plurality of the three-level power semiconductor modules of the combination of Lu and Hattori with their longitudinal sides next to one another in a row, wherein the DC voltage terminal elements of all the three-level power semiconductor modules are also arranged in a row, as taught by Kobolla, because such an in-line arrangement of modules is well-known to facilitate the implementation of multi-phase (e.g., three-phase) inverter/rectifier systems and to enable simple, low-inductance connection to common DC busbar structures (see [0020] of Kobolla).
Regarding claim 15, Lu does not disclose wherein each of the respective DC voltage terminal elements are connected in a polarity-appropriate manner to common, respectively assigned DC voltage supply line elements of a DC voltage supply line device. However, Kobolla teaches (see Figs. 1, 6, and 7) wherein each of the respective DC voltage terminal elements are connected in a polarity-appropriate manner to common, respectively assigned DC voltage supply line elements of a DC voltage supply line device (see Figs. 1 and 6 and [0038]-[0039] of Kobolla "a first DC voltage connecting element 60 ... is connected to the first DC voltage terminal element 50 in a planar fashion ... a second DC voltage connecting element 62 ... is connected to the second DC voltage terminal element 52 in a planar fashion"). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the plurality of the three-level power semiconductor modules of the combination of Lu and Hattori wherein each of the respective DC voltage terminal elements are connected in a polarity-appropriate manner to common, respectively assigned DC voltage supply line elements of a DC voltage supply line device, as taught by Kobolla, because such an in-line arrangement of modules is well-known to facilitate the implementation of multi-phase (e.g., three-phase) inverter/rectifier systems and to enable simple, low-inductance connection to common DC busbar structures (see [0020] of Kobolla).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2019/0149064 A1 discloses a multiple-level switching unit comprising four series-connected switches. US 2023/0317685 A1 discloses a packaged electronic device comprising a plurality of power transistors arranged in series-connected branches sandwiched between two DBC substrate elements forming a multi-branch power module. US 12,261,543 B2 discloses a three-level power module with a molded package, three DC power terminals (positive, neutral, negative) protruding from a first side of the molded package, and a phase output power terminal protruding from a second side of the molded package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
Prosecution Insights