CTNF 18/896,759 CTNF 96639 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION The instant application having Application No. 18/896,759 is presented for examination by the examiner. Claims 1-20 have been examined. Claim Rejections - 35 USC § 101 07-04 AIA 07-04-01 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefore, subject to the conditions and requirements of this title. Claims 17–20 are rejected under 35 U.S.C. § 101 because the claimed invention encompasses a signal per se, which does not fall within any of the four statutory categories of patentable subject matter: namely, a process, machine, manufacture, or composition of matter. The claims recite a “machine-readable medium having program code stored thereon,” which, under its broadest reasonable interpretation, encompasses transitory computer-readable communication media such as carrier waves, infrared signals, digital signals, and other forms of propagated signals. Such signals per se are not patent-eligible subject matter. While the specification contains language at paragraphs [0100]–[0101] referencing “non-transitory, tangible arrangements” and “non-transitory, tangible machine-readable media,” the specification at paragraph [0169] explicitly contemplates and discloses transitory computer machine-readable communication media as part of the invention, stating that electronic devices “store and communicate code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media... and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals such as carrier waves, infrared signals, digital signals, etc.).” Because the specification itself encompasses transitory communication media as a form of machine-readable media, the non-transitory language found elsewhere in the specification does not sufficiently limit the scope of the claims to exclude signals per se. Therefore, claims 17–20 read on non-statutory subject matter. Claim 17 recites a “machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform additional operations,” including decoding a sequence of instructions and executing a conditional instruction that outputs either a valid address value or a non-canonical address value to a destination. Because the recited “machine-readable medium” is broad enough, in view of the specification's own disclosure at paragraph [0169], to encompass transitory propagating signals such as carrier waves and electrical signals, the claim is directed to a signal per se and therefore encompasses non-statutory subject matter. Dependent claims 18–20 similarly fail to cure this deficiency. Claim 18 further limits the non-canonical address value to an invalid address value based on processor microarchitecture. Claim 19 adds arithmetic properties of the non-canonical address value, specifically that adding or multiplying a canonical value to the non-canonical address value results in further non-canonical address values. Claim 20 adds storing the non-canonical address value in a register prior to execution of the conditional instruction. None of these additional limitations restrict the "machine-readable medium" of base claim 17 to exclude signals per se, and therefore the non-statutory subject matter defect flows through to each of claims 18–20. Applicant may overcome this rejection by amending claims 17–20 to recite a “non-transitory machine-readable medium” in place of “machine-readable medium,” thereby expressly excluding signals per se and other transitory propagating signals from the scope of the claims. Applicant is advised that such an amendment must be consistent with the specification and that the non-transitory limitation should not be used to encompass non-statutory disc-based or other transitory communication media. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-3, 9-11 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabinovitch (US 20130046961 A1), in view of Durham (US 20160092702 A1) . Regarding Claim 1 Rabinovitch discloses: A processor, comprising: decode circuitry to decode a sequence of instructions, including a conditional instruction ( Rabinovitch ¶[0034], ¶[0048]: teaches decoding instructions in a pipeline including conditional instructions such as conditional memory write instructions. ); execution circuitry to execute the conditional instruction, the execution circuitry comprising security circuitry to perform operations comprising (Rabinovitch ¶[0041], ¶[0052]: teaches execution circuitry that evaluates conditions and executes conditional instructions in the execute stage.) : outputting a valid address value indicated by the conditional instruction to a destination when a condition associated with the conditional instruction is determined to be true (Rabinovitch ¶[0027]–[0029]: teaches outputting a value to a destination when a condition associated with a conditional instruction is determined to be true, wherein an arithmetic logic unit generates a condition flag (ES), a write enable logic circuit generates a write enable signal (WS) based on the condition, and the write enable signal is asserted when the condition is true, thereby enabling transfer of write data (MWD) to memory, which constitutes outputting the value to the destination.) ; and Rabinovitch teaches a pipelined processor that executes conditional instructions by evaluating a condition and enabling or suppressing a write operation based on whether the condition is true or false. However, Rabinovitch is silent in explicitly teaching: when the condition associated with the conditional instruction is determined to be false: setting an output fault value associated with the conditional instruction to a non-canonical address value or a truncated portion of the non-canonical address value; and outputting the non-canonical address value or truncated portion of the non-canonical address value to the destination. On the other hand, Durham teaches generating and processing encoded address values that include metadata stored in unused/non-canonical bits of an address (¶[0043]–[0045]). Durham further teaches obtaining an encoded address, determining whether the address includes unused/non-canonical bits, and processing the address to produce a decoded address that is returned and used as a memory address (pointer) (¶[0053]). Durham additionally teaches that when an address is corrupted or invalid (e.g., due to manipulation or invalid metadata), the resulting address causes a fault condition (¶[0025], ¶[0053]). Thus, Durham teaches setting an address value to an invalid or non-canonical form and outputting that value for use in a memory access operation, wherein the invalid or corrupted address results in a fault. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Rabinovitch such that, when the condition associated with the conditional instruction is determined to be false, instead of canceling the write operation, an invalid address value is generated and output as a fault value, as taught by Durham. Such a modification would have been motivated by the desire to ensure that unsuccessful or invalid execution paths result in detectable fault conditions rather than silent suppression of operations, thereby improving processor reliability, debugging capability, and system security by preventing unintended or unauthorized memory access. The substitution of a known fault triggering technique (use of invalid/non-canonical addresses) for another known technique (canceling execution) would have yielded predictable results. Regarding Claim 2 Rabinovitch teaches a pipelined processor that executes conditional instructions by evaluating a condition and enabling or suppressing a write operation based on whether the condition is true or false. However, Rabinovitch is silent in explicitly teaching: wherein the non-canonical address value comprises an invalid address value based on a microarchitecture of the processor. On the other hand, Durham teaches that address validity is determined based on processor implemented logic, including the use of unused or non-canonical bits within an address and enforcement of address constraints during execution (¶[0017]–[0018]). Durham further teaches that the validity of an address depends on whether the address falls within canonical or non-canonical ranges defined by the processor architecture (e.g. 32-bit, 64-bit, or other address ranges), and that addresses outside these architectural constraints result in invalid or corrupted address values that trigger a fault (¶[0053]). It would have been obvious to one of ordinary skill in the art at the time of the invention to utilize processor defined address validity constraints, as taught by Durham, in the system of Rabinovitch such that the invalid address value is based on processor (microarchitectural) address rules, in order to ensure that fault conditions are reliably triggered according to the processor’s design. Such a modification would have yielded predictable results, as processor architectures and their corresponding implementations define valid and invalid address ranges and enforce those constraints during execution. Regarding Claim 3 Rabinovitch teaches a pipelined processor that executes conditional instructions by evaluating a condition and enabling or suppressing a write operation based on whether the condition is true or false. However, Rabinovitch is silent in explicitly teaching: adding a canonical value to a first non-canonical address value results in a second non-canonical address value and that multiplying the first non-canonical address value by a canonical value results in a third non-canonical address value. On the other hand, Durham teaches that encoded indirect addresses, which include metadata stored in unused or non-canonical bits, may be modified by performing arithmetic operations on the encoded indirect address itself (¶[0040]). Durham further teaches that such arithmetic manipulation is permitted only within a valid range defined by the metadata, and that modifications outside the valid range result in corrupted or invalid address values that trigger a fault (¶[0023], ¶[0050], ¶[0053]). Additionally, Durham teaches multiplication of adjustment values associated with encoded addresses (¶[0045]), demonstrating that both additive and multiplicative arithmetic operations are applied to address related values. It would have been obvious to one of ordinary skill in the art at the time of the invention to apply arithmetic operations, such as addition and multiplication, to non-canonical or encoded address values in the system of Rabinovitch and Durham, and to recognize that such operations would result in further non-canonical or invalid address values when the resulting values fall outside the valid architectural or encoded range, since the same encoding and architectural constraints would continue to apply. Such a modification would have yielded predictable results, as arithmetic manipulation of constrained or invalid address values would be expected to preserve their invalidity under the same system rules. Regarding Claim 9 Claim 9 is directed to a method corresponding to the computer-implemented processor in claim 1. Claim 9 is similar in scope to claim 1 and is therefore rejected under similar rationale. Regarding Claim 10 Claim 10 is directed to a method corresponding to the computer-implemented processor in claim 2. Claim 10 is similar in scope to claim 2 and is therefore rejected under similar rationale. Regarding Claim 11 Claim 11 is directed to a method corresponding to the computer-implemented processor in claim 3. Claim 11 is similar in scope to claim 3 and is therefore rejected under similar rationale. Regarding Claim 17 Claim 17 is directed to a machine-readable medium corresponding to the computer-implemented processor in claim 1. Claim 17 is similar in scope to claim 1 and is therefore rejected under similar rationale. Regarding Claim 18 Claim 18 is directed to a machine-readable medium corresponding to the computer-implemented processor in claim 2. Claim 18 is similar in scope to claim 2 and is therefore rejected under similar rationale. Regarding Claim 19 Claim 19 is directed to a machine-readable medium corresponding to the computer-implemented processor in claim 3. Claim 19 is similar in scope to claim 3 and is therefore rejected under similar rationale . 07-21-aia AIA Claim s 4-5, 12-13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabinovitch (US 20130046961 A1), in view of Durham (US 20160092702 A1) as applied to claims 1, 9 and 17 above, and in further view Shanbhogue (US 20220197822 A1) . Regarding Claim 4 Rabinovitch in view of Durham teaches a processor that executes conditional instructions based on evaluated conditions while enforcing architecture defined address validity, such that non-canonical address values determined by the processor’s microarchitecture result in fault handling. However, Rabinovitch in view of Durham is silent in explicitly teaching a register that stores a non-canonical address value prior to execution of the conditional instruction, wherein the register is used as a source register for the conditional instruction when the condition is determined to be false. On the other hand, Shanbhogue teaches that metadata bits are stored in portions of a virtual address that are conventionally required to be canonical (¶[0047]). Shanbhogue further teaches that such metadata bits are included in address operands stored in registers (e.g., base/index registers) and are used by execution circuitry to generate virtual addresses (¶[0046]). Additionally, Shanbhogue explains that these metadata bits may contain non-canonical values and are preserved prior to canonicality processing, which is performed subsequently (¶[0048]–[0049]). Accordingly, Shanbhogue teaches storing a non-canonical address value in a register prior to execution and using that stored value as an input to execution circuitry. It would have been obvious to one of ordinary skill in the art to utilize the register-stored address values of Shanbhogue within the conditional execution framework of Rabinovitch and Durham, such that the stored non-canonical address value is used as a source operand when the condition is false, as this represents a predictable use of known processor register storage and conditional execution mechanisms to control operand usage. Regarding Claim 5 Rabinovitch in view of Durham teaches a processor that executes conditional instructions based on evaluated conditions while enforcing architecture-defined address validity, such that non-canonical address values determined by the processor’s microarchitecture result in fault handling. However, Rabinovitch in view of Durham is silent in explicitly teaching selector circuitry configured to select between a first value comprising a valid address value and a second value comprising a non-canonical address value or a truncated portion thereof based on the condition associated with the conditional instruction. On the other hand, Shanbhogue teaches execution circuitry comprising selector circuitry, such as multiplexers (e.g., elements 541, 641, 656), configured to select between different address values based on a control signal (¶[0065]–[0067], ¶[0073]–[0076]). Shanbhogue specifically discloses selecting between a first value comprising canonicalized address bits, corresponding to a valid address value, and a second value comprising original metadata bits stored in address fields, corresponding to a non-canonical address value or a portion thereof. Shanbhogue further teaches that the selection is performed based on control signals (e.g., control 547, 647, 657) which determine which value is output from the selector circuitry for use by execution circuitry prior to canonicality checking and memory operations (¶[0066]–[0067], ¶[0075]–[0076]). It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the teachings of Rabinovitch and Durham to incorporate the selector circuitry of Shanbhogue such that the execution circuitry selects a first value comprising the valid address value or a second value comprising the non-canonical address value or truncated portion of the non-canonical address value when the condition associated with the conditional instruction is determined to be true or false, respectively. Such a modification represents a predictable use of known hardware selection logic to control which operand value is used during conditional execution, thereby improving flexibility in address handling, including supporting metadata-tagged or non-canonical address representations, while maintaining correct execution behavior. Regarding Claim 12 Claim 12 is directed to a method corresponding to the computer-implemented processor in claim 4. Claim 12 is similar in scope to claim 4 and is therefore rejected under similar rationale. Regarding Claim 13 Claim 13 is directed to a method corresponding to the computer-implemented processor in claim 5. Claim 13 is similar in scope to claim 5 and is therefore rejected under similar rationale. Regarding Claim 20 Claim 20 is directed to a machine-readable medium corresponding to the computer-implemented processor in claim 4. Claim 20 is similar in scope to claim 4 and is therefore rejected under similar rationale . 07-21-aia AIA Claim s 6-8 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabinovitch (US 20130046961 A1), in view of Durham (US 20160092702 A1) as applied to claims 1 and 9 above, and in further view Henry (US 20130067202 A1) . Regarding Claim 6 Rabinovitch in view of Durham teaches a processor that executes conditional instructions based on evaluated conditions while enforcing architecture-defined address validity, such that non-canonical address values determined by the processor’s microarchitecture result in fault handling. However, Rabinovitch in view of Durham is silent in explicitly teaching that the conditional instruction comprises a conditional load instruction to load a valid address value from a cache-memory subsystem or a conditional move instruction to move the valid address value from a register when the condition is determined to be true. On the other hand, Henry teaches a processor microarchitecture including a set of instructions such as load/store instructions and, more specifically, conditional move instructions that move a value from a source register to a destination register if a condition is satisfied (¶[0057], Table 2). Henry further teaches that such conditional instructions are executed based on condition evaluation, such that the movement of the value occurs when the condition is true and is suppressed when the condition is false, thereby providing conditional data movement within the processor pipeline. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the processor of Rabinovitch in view of Durham to include the conditional move functionality as taught by Henry , such that the conditional instruction comprises a conditional move instruction that moves a value from a register when the condition is satisfied, in order to improve execution efficiency and avoid branch instructions. Such a modification would have yielded predictable results, as conditional move instructions are well known techniques for reducing branch misprediction penalties and enabling streamlined conditional execution in pipelined processor architectures. Regarding Claim 7 Rabinovitch in view of Durham teaches a processor that executes conditional instructions based on evaluated conditions while enforcing architecture-defined address validity, such that non-canonical address values determined by the processor’s microarchitecture result in fault handling. However, Rabinovitch in view of Durham is silent in explicitly teaching that the condition associated with the conditional instruction comprises a result of a comparison operation between a first source value and a second source value. On the other hand, Henry teaches a processor architecture supporting conditional instructions that operate on source operands supplied from general purpose registers, wherein an operation is performed on the source operands to generate a result (¶[0112], ¶[0115]). Henry further teaches that conditional instructions are executed based on condition flags such as zero, greater than, or not equal (¶[0112]), which are generated based on operations performed on multiple source operands. Thus, Henry teaches that the condition controlling execution of the conditional instruction is derived from an operation between a first source value and a second source value. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the processor of Rabinovitch in view of Durham to utilize condition generation based on comparison operations between source operands as taught by Henry , such that the condition associated with the conditional instruction is derived from a comparison between a first source value and a second source value in order to enable flexible and standard conditional execution based on operand relationships. Such a modification would have yielded predictable results, as generating condition flags from comparisons between operands is a fundamental and well-known technique in processor architectures for controlling conditional instruction execution. Regarding Claim 8 Rabinovitch in view of Durham teaches a processor that executes conditional instructions based on evaluated conditions while enforcing architecture-defined address validity, such that non-canonical address values determined by the processor’s microarchitecture result in fault handling. However, Rabinovitch in view of Durham is silent in explicitly teaching that the condition associated with the conditional instruction comprises a result of a comparison operation between a first source value and a second source value. On the other hand, Henry teaches a processor architecture supporting conditional instructions that operate on source operands supplied from general purpose registers, wherein an operation is performed on the source operands to generate a result (¶[0112], ¶[0115]). Henry further teaches that conditional instructions are executed based on condition flags such as zero, greater than, or not equal (¶[0112]), which are generated based on operations performed on multiple source operands. Thus, Henry teaches that the condition controlling execution of the conditional instruction is derived from an operation (e.g., comparison) between a first source value and a second source value. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the processor of Rabinovitch in view of Durham to utilize condition generation based on comparison operations between source operands as taught by Henry, such that the condition associated with the conditional instruction is derived from a comparison between a first source value and a second source value, in order to enable flexible and standard conditional execution based on operand relationships. Such a modification would have yielded predictable results, as generating condition flags from comparisons between operands is a fundamental and well known technique in processor architectures for controlling conditional instruction execution. Regarding Claim 14 Claim 14 is directed to a method corresponding to the computer-implemented processor in claim 6. Claim 14 is similar in scope to claim 6 and is therefore rejected under similar rationale. Regarding Claim 15 Claim 15 is directed to a method corresponding to the computer-implemented processor in claim 7. Claim 15 is similar in scope to claim 7 and is therefore rejected under similar rationale. Regarding Claim 16 Claim 16 is directed to a method corresponding to the computer-implemented processor in claim 8. Claim 16 is similar in scope to claim 8 and is therefore rejected under similar rationale. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAAD ABDULLAH whose telephone number is 571-272-1531. The examiner can normally be reached on Monday-Friday 9am-5pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, LYNN FIELD can be reached on 571-272-2092. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAAD AHMAD ABDULLAH/ Examiner, Art Unit 2431 /SHIN-HON (ERIC) CHEN/ Primary Examiner, Art Unit 2431 Application/Control Number: 18/896,759 Page 2 Art Unit: 2431 Application/Control Number: 18/896,759 Page 3 Art Unit: 2431 Application/Control Number: 18/896,759 Page 4 Art Unit: 2431 Application/Control Number: 18/896,759 Page 5 Art Unit: 2431 Application/Control Number: 18/896,759 Page 6 Art Unit: 2431 Application/Control Number: 18/896,759 Page 7 Art Unit: 2431 Application/Control Number: 18/896,759 Page 8 Art Unit: 2431 Application/Control Number: 18/896,759 Page 9 Art Unit: 2431 Application/Control Number: 18/896,759 Page 10 Art Unit: 2431 Application/Control Number: 18/896,759 Page 11 Art Unit: 2431 Application/Control Number: 18/896,759 Page 12 Art Unit: 2431 Application/Control Number: 18/896,759 Page 13 Art Unit: 2431 Application/Control Number: 18/896,759 Page 14 Art Unit: 2431 Application/Control Number: 18/896,759 Page 15 Art Unit: 2431 Application/Control Number: 18/896,759 Page 16 Art Unit: 2431
Prosecution Insights