DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed January 22, 2026. The applicant’s remarks and amendment to the specification and/or claims were considered with the results that follow.
Claims 2-21 have been presented for examination in this application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2 and 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Palmer (US# 10,725,930).
Regarding claim 2, Palmer teaches an apparatus, comprising: processing circuitry configured to cause the apparatus to: select a portion of a node address mapping stored in a first area of a non- volatile memory device of a memory system, the memory system having the non-volatile memory device and a volatile memory device [col. 2, lines 19-29 & 30-36]; transmit a command to transfer the portion of the node address mapping to the volatile memory device that is associated with firmware of the memory system, the node address mapping comprising one or more addresses associated with node blocks of a second area of the non-volatile memory device [col. 2, lines 36-42 & col. 5, lines 37-45]; and receive a response to the command, the response indicating a status associated with transferring the portion [col. 7, lines 27-32; node indication].
Claims 13 and 15 recite language similar to that of claim 2, and are rejected for the same reasons as claim 2.
Regarding claim 14, Palmer teaches wherein the non-volatile memory device is associated with a file system layout, the file system layout indicating an index for each area of the plurality of areas, the plurality of areas comprising the first area storing the node address mapping, the second area storing data associated with a host system, a third area storing checkpoint data, a fourth area storing a segment information table, a fifth area storing a segment summary area, or any combination thereof [each plurality of areas is associated with a portion of the L2P table [col. 2, lines 14-36].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5, 7-11, 16-18, 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer in view of Zhou et al. (US# 2021/0096939).
Regarding claim 3, Palmer teaches an associated status relative to address availability but fails to teach wherein the status comprises a successful status indicating that the memory system transferred the portion of the node address mapping to the volatile memory device. Zhou teaches indicating a successful status upon transferal to the volatile memory of the mapping portion [0089]. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Palmer to include expanded responses because then a means for detecting normal and abnormal response could be implemented [0012].
Regarding claim 4, Zhou et al. teaches wherein the status comprises a busy status indicating that the memory system is processing one or more operations associated with one or more commands sent prior to the command to transfer the portion [0030; timeout].
Regarding claim 5, Zhou et al. teaches wherein the status comprises a failed status indicating that the memory system failed to transfer the portion of the node address mapping [0011].
Regarding claim 7, Zhou et al. teaches wherein the processing circuitry is further configured to cause the apparatus to: receive an indication of one or more parameters associated with the failed status in the response, the one or more parameters associated with an illegal request, a hardware error, a power threshold, or any combination thereof [0074, hardware failure].
Regarding claim 8, Palmer teaches, wherein the processing circuitry is further configured to cause the apparatus to: fill one or more fields of the command in response to selecting the portion of the node address mapping, the one or more fields indicating the portion of the node address mapping [Palmer, col. 6, lines 55-65].
Regarding claim 9, Palmer teaches wherein the one or more fields indicate a range of addresses associated with the node address mapping or a portion of the range of addresses [col. 8, lines 35-42; LBA writing].
Regarding claim 10, Palmer teaches wherein the processing circuitry is further configured to cause the apparatus to: transmit a second command to remove a second portion of the node address mapping from the volatile memory device [col. 9, lines 25-50; claim may also be interpreted as second portion to be removed may correspond to new command/address].
Regarding claim 11, Zhou et al. teaches, wherein the command comprises an indication of a type of information associated with the portion of the node address mapping [col. 8, lines 35-42, where sequential access comprises LBA +length parameter].
Claim 16 recites language similar to that of claim 3, and is rejected for the same reasons as claim 3.
Claim 17 recites language similar to that of claim 4, and is rejected for the same reasons as claim 4.
Claim 18 recites language similar to that of claim 5, and is rejected for the same reasons as claim 5.
Claim 20 recites language similar to that of claim 7, and is rejected for the same reasons as claim 7.
Claim 21 recites language similar to that of claim 8, and is rejected for the same reasons as claim 8.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US# 10,725,930) in view of Zhou et al. (US# 2021/0096939) as applied to claims 3-5, 7-11, 16-18, 20 and 21 above, and further in view of Bannerjee et al. (US# 8,868,839).
Regarding claim 12, the combination of Palmer and Zhou fails to teach identifying that the portion of the node address mapping corresponds to a frequency of access operations that satisfies a threshold, wherein selecting the portion is in accordance with the satisfied threshold. Bannerjee teaches this selection at col. 9, lines 4-16. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Palmer and Zhou to include the threshold system of Bannerjee in order to facilitate expedited data access [col. 1, lines 20-30].
Response to Arguments
Applicant’s arguments with respect to the Double Patenting rejection have been fully considered and are persuasive. The Double Patenting rejection has been withdrawn.
Applicant's arguments filed January 22, 2026, directed towards the 35 USC 102 and 103 rejections, have been fully considered but they are not persuasive.
Regarding Applicant’s argument on page 8,
Palmer does not disclose at least "transmit a command to transfer the portion of the node address mapping to the volatile memory device that is associated with firmware of the memory system" or "receive a response to the command, the response indicating a status associated with transferring the portion,",
the Examiner respectfully disagrees. According to Palmer, col. 2, lines 29-39, the address mapping table may comprise several portions which may be stored in non-volatile memory, and that these portions may be cached in volatile memory SRAM. Furthermore, this swapping of table portions is “for access and use by a memory sub-system controller as needed”. Needs of the controller necessitate the swapping of table portions between volatile and non-volatile memory, and as one of ordinary skill in the art would recognize, memories on their own are unable to move data and inherently require commands transmitted from a processing circuitry to a controlling device of a memory to direct the movement of data from a source to a destination.
The claimed “receive a response to the command” is broadly written, and a broad and reasonable interpretation of the claim limitation language would indicate that the status, which is “associated” with transferring the portion, may relate to a status that indicates that the command is received, the command is rejected , the command is being processed, the command has failed, the command has finished, or any other status that is in any way “associated” with the transmission of the command, including the completion of the original memory operation. As also seen in column 2, lines 21-29, the controller receives a command that requires movement of at least one logical address before the command can be successfully executed, thus the response to the command being at least the successful execution of the command.
Allowable Subject Matter
Claims 6 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian R. Peugh whose telephone number is (571) 272-4199. The examiner can normally be reached on Monday-Friday from 7:30am to 3:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rocio Del Mar Perez-Velez, phone number 571-270-5935, can be reached. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BRIAN R PEUGH/ Primary Examiner, Art Unit 2133
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