DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is in response to the following communication: Non-provisional Application No. 18/896,885 filed on 09/25/2024.
3. Claims 1-20 are pending.
Claims 1, 8 and 15 are independent claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Regarding claims 1, 8 and 15, the limitations “translate the first binary words to second binary words” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. These limitations encompass a human mind carrying out these functions through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Claims 1, 8 and 15: Under Prong 2 Step 2A, the judicial exception is not integrated into a practical application. The additional elements “a processor”, “a dynamic translation unit”, “a processor core”, “a storage medium”, and “a processing device” merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea, thus is not a practical application under Prong 2. The additional element “receive first binary words”, “translation are performed within a pipeline“, and “binary word are processed in encrypted format“ do nothing more than add insignificant extra solution activity to the judicial exception of merely gathering data. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f) and (g), respectively.
Claims 1, 8 and 15: Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As stated above in prong 2, the additional elements “a processor”, “a dynamic translation unit”, “a processor core”, “a storage medium”, and “a processing device” merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea, and the additional element “receive first binary words”, “translation are performed within a pipeline“, and “binary word are processed in encrypted format“ is merely gathering data which the courts have identified as well-understood, routine conventional activity. See for example Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362, MPEP 2106.05(d). Therefore, the additional elements do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101.
Claims 1, 8 and 15 recite further additional elements “a processor”, “a dynamic translation unit”, “a processor core”, “a storage medium”, and “a processing device”. These additional elements are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computer, and/or generic computer components. See MPEP 2106.05(f). Therefore, the additional elements recited in claims 1, 8 and 15 do not integrate the judicial exception into a practical application under prong 2, nor amount to significantly more under step 2B.,
Regarding claims 2-7, 9-13 and 16-20, the additional elements of “subunits arranged in parallel”, “DTU comprises two data ports and two control ports”, “binary words are encrypted ”, “plurality of subunits share storage resources”, “DTU is contained within a pipeline”, “first machine code language is Complex Instruction Set Computer”, “second machine code is Reduced Instruction Set Computer”, “receiving is performed by a dynamic translation unit”, “data within the pipeline remains encrypted”, “sharing storage resources”, “binary words are received”, and “each of the first binary words are received” is analyzed under Prong 2 as mere data gathering which does not integrate the judicial exception into a practical application, or amounts to significantly more under Step 2B for the reasons provided in the rejection of claims 1, 6 and 11.
Regarding claim 14, the limitation “translate the first binary words to second binary words” recites additional mental process under Prong 1. The additional element “receive first binary words”, “receiving and the translation are performed”, and “first binary word and the second binary word are processed” is analyzed under Prong 2 as mere data gathering which does not integrate the judicial exception into a practical application, or amounts to significantly more under Step 2B for the reasons provided in the rejection of claims 1, 6 and 11.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-3 and 5-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kelm et al., US 20170242705 (hereinafter Kelm).
In regards to claim 1, Kelm teaches:
A processor, comprising: a dynamic translation unit (DTU) configured to receive first binary words associated with a first machine code language instruction set from a memory unit of the processor and translate the first binary words to second binary words associated with a second machine code language (p. 5, [0068]), see “an instruction in accordance with one embodiment may be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc.”, (p. 14, [0134]), see a strand may include a sequence of instructions that are data dependent upon each other” and (p. 16, [0155]), see Binary translator 1844 may read a sequence of guest code and generate a sequence of host code as a result of translation. When executed, the host code should have the same effect as if the guest code were executed directly. Accordingly, system 1800 may preserve equivalent functionality of translated code and the original code”.
In regards to claim 2, Kelm teaches:
the DTEU comprises a plurality of subunits arranged in parallel (p. 19, [0186]), see “at 2005, it may be determined that a translation of code will be made. Such translation may be performed by, for example, binary translator 1844. At 2010, T-bit protection may be set for the region of memory that is to be translated. T-bit protection may be made by setting bits within PHYSMAP 1822 or a local, cached version of its contents. At 2015, drains of other SSBs on other cores may be requested. In one embodiment, 2010 and 2015 may be performed in parallel or in a different order”.
In regards to claim 3, Kelm teaches:
the DTU comprises two data ports and two control ports (p. 9, [0088]), see “memory access units 464 may include a load unit, a store address unit, and a store data unit, each of which may be coupled to data TLB unit 472 in memory unit 470” and (p. 14, [0137]), see "unit 1510 may perform bus interfacing to other portions of a processor or electronic device. In such an embodiment, unit 1510 may thus include a bus interface unit 1520 for communicating over an interconnect, intraprocessor bus, or other communication bus, port, or line. Bus interface unit 1520 may provide interfacing in order to perform, for example, generation of the memory and input/output addresses for the transfer of data between execution entities 1565 and the portions of a system external to instruction architecture 1500".
In regards to claim 5, Kelm teaches:
the plurality of subunits share storage resources (p. 10, [0103]), see "parallel execution in core 502 may be performed by any suitable number of separate execution blocks or virtual processors. In one embodiment, shared resources—such as memory, registers, and caches—may be accessible to multiple virtual processors within a given core 502. In other embodiments, shared resources may be accessible to multiple processing entities within processor 500".
In regards to claim 6, Kelm teaches:
the DTU is contained within a pipeline of a processing core of the processor (p. 15, [0145]), see "FIG. 16 is a block diagram of an execution pipeline 1600 for a processor, in accordance with embodiments of the present disclosure. Execution pipeline 1600 may illustrate operation of, for example, instruction architecture 1500 of FIG. 15", (p. 16, [0153]), see processor 1802 may include a binary translator 1844 communicatively coupled to an uncore 1806 and one or more cores 1808. In another embodiment, binary translator 1844 may be included within system 1800 but outside of processor 1800. Binary translator 1844 may be implemented in any suitable manner. In one embodiment, binary translator 1844 may be implemented by a hardware device, including a finite state machine and logic implemented in processor 1802” and (p. 17, [0159]), see "each of cores 1808 may be designed to execute code written in a particular coding language. In order to have a program executed by cores 1808, program code may need to be translated from a first coding language that is incompatible with the particular core to a second coding language that is compatible with the particular core. Such translation may be performed by binary translator 1844".
In regards to claim 7, Kelm teaches:
the first machine code language is Complex Instruction Set Computer (CISC) and the second machine code is Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC). (p. 5, [0068]), see "in one embodiment, the decoder decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called micro op or uops) that the machine may execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, trace cache 230 may assemble decoded uops into program ordered sequences or traces in uop queue 234 for execution. When trace cache 230 encounters a complex instruction, microcode ROM 232 provides the uops needed to complete the operation” and (p. 8, [0085]), see "core 490 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type".
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 4 and 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kelm in view of Maniatakos et al., US 2015/0193628 (hereinafter Maniatakos).
In regards to claim 1, the rejections above are incorporated respectively.
In regards to claim 4, Kelm doesn’t explicitly teach:
the binary words are encrypted during translation to the second machine code language.
However, Maniatakos teaches such use: (p. 6, [0054]), see “the HEROIC RTL implementation presented in the previous paragraphs provides protection against eavesdropping, but requires processor that is natively capable of processing in the HEROIC computing architecture 200 (i.e., an FPGA). To overcome this hardware constraint, a virtual machine may be leveraged, which generally provides a translation layer for porting one ISA over another. Accordingly, a HEROIC Virtual Machine (“VM”) can provide the HEROIC computing architecture 200 and be the basis for the cloud computing system 102, which can be run on any commodity CPU. In some arrangements, the VM is implemented in C and runs natively (i.e. without emulating any hardware states or modules) using the GNU GMP multiple precision arithmetic library that is portable and already optimized for performance on different CPU architectures. The implemented VM is capable of executing encrypted HEROIC programs, receiving encrypted inputs at runtime, and generating encrypted outputs to program owners”.
Kelm and Maniatakos are analogous art because they are from the same field of endeavor, code translations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kelm and Maniatakos before him or her, to modify the system of Kelm to include the teachings of Maniatakos, as a system for encrypted instruction computation and accordingly it would enhance the system of Kelm, which is focused on support for code modification, because that would provide Kelm with the ability to protecting the confidentiality of the information processed in a more definitive and effective manner.as suggested by Maniatakos (p. 6, [0054]), p. 7, [0064]).
In regards to claim 8, Kelm teaches:
A method, comprising: receiving first binary words associated with a first machine code language instruction set; and translating the first binary words to second binary words associated with a second machine code language (p. 5, [0068]), see “an instruction in accordance with one embodiment may be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc.”, (p. 14, [0134]), see a strand may include a sequence of instructions that are data dependent upon each other” and (p. 16, [0155]), see Binary translator 1844 may read a sequence of guest code and generate a sequence of host code as a result of translation. When executed, the host code should have the same effect as if the guest code were executed directly. Accordingly, system 1800 may preserve equivalent functionality of translated code and the original code”.
the receiving and the translation are performed within a pipeline of a processor core (p. 16, [0155]), see "binary translator 1844 may read a sequence of guest code and generate a sequence of host code as a result of translation. When executed, the host code should have the same effect as if the guest code were executed directly", (p. 8, [0083]), see “in FIG. 4A, a processor pipeline 400 may include a fetch stage 402, a length decode stage 404, a decode stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also known as a dispatch or issue) stage 412, a register read/memory read stage 414, an execute stage 416, a write-back/memory-write stage 418, an exception handling stage 422, and a commit stage 424” and (p. 14, [0134]), see "in one embodiment, memory system 1540 may include an executed instruction pointer 1580. Executed instruction pointer 1580 may store a value identifying the oldest, undispatched instruction within a batch of instructions in the out-of-order issue stage 1560 within a thread represented by multiple strands. Executed instruction pointer 1580 may be calculated in issue stage 1560 and propagated to load units. The instruction may be stored within a batch of instructions... The strand may be arranged by a binary translator at compilation time. Hardware executing a strand may execute the instructions of a given strand in order according to PO of the various instructions. A thread may include multiple strands such that instructions of different strands may depend upon each other”.
Kelm doesn’t explicitly teach:
the first binary word and the second binary word are processed in encrypted format during the receiving and the translating.
However, Maniatakos teaches such use: (p. 6, [0054]), see “the HEROIC RTL implementation presented in the previous paragraphs provides protection against eavesdropping, but requires processor that is natively capable of processing in the HEROIC computing architecture 200 (i.e., an FPGA). To overcome this hardware constraint, a virtual machine may be leveraged, which generally provides a translation layer for porting one ISA over another. Accordingly, a HEROIC Virtual Machine (“VM”) can provide the HEROIC computing architecture 200 and be the basis for the cloud computing system 102, which can be run on any commodity CPU. In some arrangements, the VM is implemented in C and runs natively (i.e. without emulating any hardware states or modules) using the GNU GMP multiple precision arithmetic library that is portable and already optimized for performance on different CPU architectures. The implemented VM is capable of executing encrypted HEROIC programs, receiving encrypted inputs at runtime, and generating encrypted outputs to program owners”.
Kelm and Maniatakos are analogous art because they are from the same field of endeavor, code translations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kelm and Maniatakos before him or her, to modify the system of Kelm to include the teachings of Maniatakos, as a system for encrypted instruction computation and accordingly it would enhance the system of Kelm, which is focused on support for code modification, because that would provide Kelm with the ability to protecting the confidentiality of the information processed in a more definitive and effective manner.as suggested by Maniatakos (p. 6, [0054]), p. 7, [0064]).
In regards to claim 9, Kelm teaches:
the first machine code language is Complex Instruction Set Computer (CISC) and the second machine code is Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) (p. 5, [0068]), see "in one embodiment, the decoder decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called micro op or uops) that the machine may execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, trace cache 230 may assemble decoded uops into program ordered sequences or traces in uop queue 234 for execution. When trace cache 230 encounters a complex instruction, microcode ROM 232 provides the uops needed to complete the operation” and (p. 8, [0085]), see "core 490 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type".
In regards to claim 10, Kelm teaches:
the receiving is performed by a dynamic translation unit disposed between a memory unit of the pipeline and a fetch stage of the pipeline (p. 8, [0083]), see “in FIG. 4A, a processor pipeline 400 may include a fetch stage 402, a length decode stage 404, a decode stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also known as a dispatch or issue) stage 412, a register read/memory read stage 414, an execute stage 416, a write-back/memory-write stage 418, an exception handling stage 422, and a commit stage 424”.
In regards to claim 11, Kelm doesn’t explicitly teach:
data within the pipeline remains encrypted throughout processing within the pipeline.
However, Maniatakos teaches such use: (p. 6, [0054]), see “the HEROIC RTL implementation presented in the previous paragraphs provides protection against eavesdropping, but requires processor that is natively capable of processing in the HEROIC computing architecture 200 (i.e., an FPGA). To overcome this hardware constraint, a virtual machine may be leveraged, which generally provides a translation layer for porting one ISA over another. Accordingly, a HEROIC Virtual Machine (“VM”) can provide the HEROIC computing architecture 200 and be the basis for the cloud computing system 102, which can be run on any commodity CPU. In some arrangements, the VM is implemented in C and runs natively (i.e. without emulating any hardware states or modules) using the GNU GMP multiple precision arithmetic library that is portable and already optimized for performance on different CPU architectures. The implemented VM is capable of executing encrypted HEROIC programs, receiving encrypted inputs at runtime, and generating encrypted outputs to program owners”.
Kelm and Maniatakos are analogous art because they are from the same field of endeavor, code translations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kelm and Maniatakos before him or her, to modify the system of Kelm to include the teachings of Maniatakos, as a system for encrypted instruction computation and accordingly it would enhance the system of Kelm, which is focused on support for code modification, because that would provide Kelm with the ability to protecting the confidentiality of the information processed in a more definitive and effective manner.as suggested by Maniatakos (p. 6, [0054]), p. 7, [0064]).
In regards to claim 12, Kelm teaches:
sharing storage resources when translating the first binary words (p. 10, [0103]), see "parallel execution in core 502 may be performed by any suitable number of separate execution blocks or virtual processors. In one embodiment, shared resources—such as memory, registers, and caches—may be accessible to multiple virtual processors within a given core 502. In other embodiments, shared resources may be accessible to multiple processing entities within processor 500".
In regards to claim 13, Kelm teaches:
each of the first binary words are received into a corresponding subunit of a translation unit (p. 7, [0074]), see "in one embodiment, integer registers store 32-bit integer data. A register file of one embodiment also contains eight multimedia SIMD registers for packed data".
In regards to claim 14, Kelm teaches:
a maximum of 8 binary words are received per cycle (p. 7, [0076]), see "although the data types illustrated in FIG. 3A may be 128 bits long, embodiments of the present disclosure may also operate with 64-bit wide or other sized operands. Packed word format 320 of this example may be 128 bits long and contains eight packed word data elements".
receive first binary words associated with a first machine code language instruction set; and translate the first binary words to second binary words associated with a second machine code language (p. 5, [0068]), see “an instruction in accordance with one embodiment may be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc.”, (p. 14, [0134]), see a strand may include a sequence of instructions that are data dependent upon each other” and (p. 16, [0155]), see Binary translator 1844 may read a sequence of guest code and generate a sequence of host code as a result of translation. When executed, the host code should have the same effect as if the guest code were executed directly. Accordingly, system 1800 may preserve equivalent functionality of translated code and the original code”.
the receiving and the translation are performed within a pipeline of a processor core (p. 16, [0155]), see "binary translator 1844 may read a sequence of guest code and generate a sequence of host code as a result of translation. When executed, the host code should have the same effect as if the guest code were executed directly", (p. 8, [0083]), see “in FIG. 4A, a processor pipeline 400 may include a fetch stage 402, a length decode stage 404, a decode stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also known as a dispatch or issue) stage 412, a register read/memory read stage 414, an execute stage 416, a write-back/memory-write stage 418, an exception handling stage 422, and a commit stage 424” and (p. 14, [0134]), see "in one embodiment, memory system 1540 may include an executed instruction pointer 1580. Executed instruction pointer 1580 may store a value identifying the oldest, undispatched instruction within a batch of instructions in the out-of-order issue stage 1560 within a thread represented by multiple strands. Executed instruction pointer 1580 may be calculated in issue stage 1560 and propagated to load units. The instruction may be stored within a batch of instructions... The strand may be arranged by a binary translator at compilation time. Hardware executing a strand may execute the instructions of a given strand in order according to PO of the various instructions. A thread may include multiple strands such that instructions of different strands may depend upon each other”.
Kelm doesn’t explicitly teach:
the first binary word and the second binary word are processed in encrypted format during the receiving and the translating.
However, Maniatakos teaches such use: (p. 6, [0054]), see “the HEROIC RTL implementation presented in the previous paragraphs provides protection against eavesdropping, but requires processor that is natively capable of processing in the HEROIC computing architecture 200 (i.e., an FPGA). To overcome this hardware constraint, a virtual machine may be leveraged, which generally provides a translation layer for porting one ISA over another. Accordingly, a HEROIC Virtual Machine (“VM”) can provide the HEROIC computing architecture 200 and be the basis for the cloud computing system 102, which can be run on any commodity CPU. In some arrangements, the VM is implemented in C and runs natively (i.e. without emulating any hardware states or modules) using the GNU GMP multiple precision arithmetic library that is portable and already optimized for performance on different CPU architectures. The implemented VM is capable of executing encrypted HEROIC programs, receiving encrypted inputs at runtime, and generating encrypted outputs to program owners”.
Kelm and Maniatakos are analogous art because they are from the same field of endeavor, code translations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kelm and Maniatakos before him or her, to modify the system of Kelm to include the teachings of Maniatakos, as a system for encrypted instruction computation and accordingly it would enhance the system of Kelm, which is focused on support for code modification, because that would provide Kelm with the ability to protecting the confidentiality of the information processed in a more definitive and effective manner.as suggested by Maniatakos (p. 6, [0054]), p. 7, [0064]).
In regards to claim 15, Kelm teaches:
A non-transitory computer readable storage medium storing instructions, which when executed, cause a processing device to: receive first binary words associated with a first machine code language instruction set; and translate the first binary words to second binary words associated with a second machine code language (p. 5, [0068]), see “an instruction in accordance with one embodiment may be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc.”, (p. 14, [0134]), see a strand may include a sequence of instructions that are data dependent upon each other” and (p. 16, [0155]), see Binary translator 1844 may read a sequence of guest code and generate a sequence of host code as a result of translation. When executed, the host code should have the same effect as if the guest code were executed directly. Accordingly, system 1800 may preserve equivalent functionality of translated code and the original code”.
the receiving and the translation are performed within a pipeline of a processor core (p. 16, [0155]), see "binary translator 1844 may read a sequence of guest code and generate a sequence of host code as a result of translation. When executed, the host code should have the same effect as if the guest code were executed directly", (p. 8, [0083]), see “in FIG. 4A, a processor pipeline 400 may include a fetch stage 402, a length decode stage 404, a decode stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also known as a dispatch or issue) stage 412, a register read/memory read stage 414, an execute stage 416, a write-back/memory-write stage 418, an exception handling stage 422, and a commit stage 424” and (p. 14, [0134]), see "in one embodiment, memory system 1540 may include an executed instruction pointer 1580. Executed instruction pointer 1580 may store a value identifying the oldest, undispatched instruction within a batch of instructions in the out-of-order issue stage 1560 within a thread represented by multiple strands. Executed instruction pointer 1580 may be calculated in issue stage 1560 and propagated to load units. The instruction may be stored within a batch of instructions... The strand may be arranged by a binary translator at compilation time. Hardware executing a strand may execute the instructions of a given strand in order according to PO of the various instructions. A thread may include multiple strands such that instructions of different strands may depend upon each other”.
Kelm doesn’t explicitly teach:
the first binary word and the second binary word are processed in encrypted format during the receiving and the translating.
However, Maniatakos teaches such use: (p. 6, [0054]), see “the HEROIC RTL implementation presented in the previous paragraphs provides protection against eavesdropping, but requires processor that is natively capable of processing in the HEROIC computing architecture 200 (i.e., an FPGA). To overcome this hardware constraint, a virtual machine may be leveraged, which generally provides a translation layer for porting one ISA over another. Accordingly, a HEROIC Virtual Machine (“VM”) can provide the HEROIC computing architecture 200 and be the basis for the cloud computing system 102, which can be run on any commodity CPU. In some arrangements, the VM is implemented in C and runs natively (i.e. without emulating any hardware states or modules) using the GNU GMP multiple precision arithmetic library that is portable and already optimized for performance on different CPU architectures. The implemented VM is capable of executing encrypted HEROIC programs, receiving encrypted inputs at runtime, and generating encrypted outputs to program owners”.
Kelm and Maniatakos are analogous art because they are from the same field of endeavor, code translations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kelm and Maniatakos before him or her, to modify the system of Kelm to include the teachings of Maniatakos, as a system for encrypted instruction computation and accordingly it would enhance the system of Kelm, which is focused on support for code modification, because that would provide Kelm with the ability to protecting the confidentiality of the information processed in a more definitive and effective manner.as suggested by Maniatakos (p. 6, [0054]), p. 7, [0064]).
In regards to claim 16, Kelm teaches:
the first machine code language is Complex Instruction Set Computer (CISC) and the second machine code is Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) (p. 5, [0068]), see "in one embodiment, the decoder decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called micro op or uops) that the machine may execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, trace cache 230 may assemble decoded uops into program ordered sequences or traces in uop queue 234 for execution. When trace cache 230 encounters a complex instruction, microcode ROM 232 provides the uops needed to complete the operation” and (p. 8, [0085]), see "core 490 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type".
In regards to claim 17, Kelm teaches:
the receiving is performed by a dynamic translation unit disposed between a memory unit of the pipeline and a fetch stage of the pipeline (p. 8, [0083]), see “in FIG. 4A, a processor pipeline 400 may include a fetch stage 402, a length decode stage 404, a decode stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also known as a dispatch or issue) stage 412, a register read/memory read stage 414, an execute stage 416, a write-back/memory-write stage 418, an exception handling stage 422, and a commit stage 424”.
In regards to claim 18, Kelm doesn’t explicitly teach:
data within the pipeline remains encrypted throughout processing within the pipeline.
However, Maniatakos teaches such use: (p. 6, [0054]), see “the HEROIC RTL implementation presented in the previous paragraphs provides protection against eavesdropping, but requires processor that is natively capable of processing in the HEROIC computing architecture 200 (i.e., an FPGA). To overcome this hardware constraint, a virtual machine may be leveraged, which generally provides a translation layer for porting one ISA over another. Accordingly, a HEROIC Virtual Machine (“VM”) can provide the HEROIC computing architecture 200 and be the basis for the cloud computing system 102, which can be run on any commodity CPU. In some arrangements, the VM is implemented in C and runs natively (i.e. without emulating any hardware states or modules) using the GNU GMP multiple precision arithmetic library that is portable and already optimized for performance on different CPU architectures. The implemented VM is capable of executing encrypted HEROIC programs, receiving encrypted inputs at runtime, and generating encrypted outputs to program owners”.
Kelm and Maniatakos are analogous art because they are from the same field of endeavor, code translations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kelm and Maniatakos before him or her, to modify the system of Kelm to include the teachings of Maniatakos, as a system for encrypted instruction computation and accordingly it would enhance the system of Kelm, which is focused on support for code modification, because that would provide Kelm with the ability to protecting the confidentiality of the information processed in a more definitive and effective manner.as suggested by Maniatakos (p. 6, [0054]), p. 7, [0064]).
In regards to claim 19, Kelm teaches:
a maximum of 8 binary words are received per cycle (p. 7, [0076]), see "although the data types illustrated in FIG. 3A may be 128 bits long, embodiments of the present disclosure may also operate with 64-bit wide or other sized operands. Packed word format 320 of this example may be 128 bits long and contains eight packed word data elements".
In regards to claim 20, Kelm teaches:
the processing device is further configured to share storage resources when translating the first binary words (p. 10, [0103]), see "parallel execution in core 502 may be performed by any suitable number of separate execution blocks or virtual processors. In one embodiment, shared resources—such as memory, registers, and caches—may be accessible to multiple virtual processors within a given core 502. In other embodiments, shared resources may be accessible to multiple processing entities within processor 500".
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publications
Morehead 10719668 teaches receive an input representation of information in the first language, convert the input representation of information in the first language to one or more sets of one or more marked-lemma dependency trees (MDTs), convert said one or more sets of one or more marked-MDTs to a representation of information in said second language, and output said representation of information in said second language, wherein the MDTs are represented in a mathematically-equivalent or isomorphic memory structure using one of word embeddings, sense embeddings, tree kernels, capsules, pose vectors, embeddings, and vectorization.
Favor 6336178 teaches an internal instruction format that facilitates translation of a very large number of CISC-type instructions into a small number of RISC-type operations. What is also needed is an internal instruction format that facilitates conversion of CISC-type instructions into a minimum number of RISC-type operations. What is further needed is an internal instruction format that permits more common CISC-type instructions to be converted using hardwired logic, as compared to conversion via lookup ROM.
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/EVRAL E BODDEN/Primary Examiner, Art Unit 2193
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