Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election of Species B in the reply filed May 6, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). Claim 2 drawn to the non-elected species has been withdrawn from examination for patentability.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In claim 1, the claimed feature that a first NMOS transistor contains a source connected to the back gate of the first PMOS transistor and a ground terminal and a second NMOS transistor contains a source connected to the back gate of the first PMOS transistor and the ground terminal is inconsistent with the specification. Fig. 2 shows a first NMOS transistor 3 and a second NMOS transistor 4 that each have a source connected to the back gate of the same NMOS transistor and the ground terminal instead. Thus, the feature has been interpreted to require a first NMOS transistor containing a source connected to the back gate of the first NMOS transistor and a ground terminal and a second NMOS transistor containing a source connected to the back gate of the second NMOS transistor and the ground terminal instead.
The term “the voltage generated between the first port and the second port” lacks proper antecedent basis.
Dependent claims 3-5 are rejected for the above-discussed reasons.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,147,548 to Doyle (cited in an IDS).
With respect to claim 1, insofar as understood, Doyle discloses in Fig. 6 a reference voltage circuit including a differential amplifier circuit, the differential amplifier circuit comprising:
a first PMOS transistor (e.g., i8) containing a gate corresponding to a first input port, a source, and a drain;
a second PMOS transistor (e.g., i6) containing a gate corresponding to a second input port, a source connected to the source of the first PMOS transistor, a back gate connected to the back gate of the first PMOS transistor (e.g., i6), and a drain;
a first NMOS transistor (e.g., i0) containing a drain connected to the drain of the first PMOS transistor (e.g., i8), a gate connected to the drain of the first NMOS transistor (e.g., i0) and the drain of the first PMOS transistor (e.g., i8), a back gate, and a source connected to the back gate of the first NMOS transistor (e.g., i0) and a ground terminal;
a second NMOS transistor (e.g., i1) containing a drain connected to the drain of the second PMOS transistor (e.g., i6), a gate connected to the drain of the second NMOS transistor (e.g., i1), a back gate, and a source connected to the back gate of the second NMOS transistor (e.g., i1) and the ground terminal; and
a voltage adjustment circuit (e.g., i17 and i15) comprising:
a first terminal (e.g., the junction between i17 and i15) connected to commonly connected sources of the first PMOS transistor and the second PMOS transistor (e.g., i8 and i6);
a second terminal (e.g., the junction between i14-i15) connected to commonly connected back gates of the first PMOS transistor and the second PMOS transistor (e.g., i8 and i6); and
a power input terminal (e.g., the source of i17) connected to a power supply terminal, the voltage adjustment circuit being configured to increase and decrease a voltage (e.g., a voltage at the junction of i17 and i15) generated between (e.g., the junction of i17 and i15 is between the gate of i8 and the gate of i6 and is generated in response to the gate voltages) the first port (e.g., the gate of i8) and the second port (e.g., the gate of i6) in response to a change in an input voltage (e.g., INB-INA) of the differential amplifier circuit.
With respect to claim 3, the voltage adjustment circuit (e.g., i17 and i15) comprises a current source (e.g., i17) connected between the power supply terminal and the second terminal (e.g., the junction between i14-i15), and a resistor (e.g., i15) connected between the first terminal (e.g., the junction between i17 and i15) and the second terminal (e.g., the junction between I14-15), and the current source (e.g., i17) is a variable current source (e.g., i17 is a transistor that changes its resistance according to POUT and as POUT changes according to changes in INB-INA, the resistance of i17 changes) configured to adjust a current value such that a voltage generated across both terminals of the resistor (e.g., i15) increases and decreases in response to a change in an input voltage of the differential amplifier circuit (e.g., i17 is a transistor that changes its resistance according to POUT and as POUT changes according to changes in INB-INA, the resistance of i17 changes).
Allowable Subject Matter
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JUNG KIM/
Primary Examiner, Art Unit 2836
Prosecution Insights