Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the documents filed on 07/30/2026. Claims 1, 8, 12 are amended on 07/27/2026. Claim 7 was amended on 07/30/2026. Claims 1 – 17 dated by 07/30/2026 are pending for consideration.
Examiner Notes
Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Response to Arguments
Corrected set of drawings is excepted. Drawing objection withdrawn.
Applicant arguments in Arguments/Remarks filed on 07/27/2026 (hereafter Remarks) referring to the Office Action on 03/25/2026 (hereafter OA) have been fully considered but they are not persuasive.
On p. 20 of the Remarks Applicant disputes claim 1 rejection under 101 arguing that claim 1 recites structural elements.
Examiner respectfully submits that according the MPEP 2111 Claims should be given their broadest reasonable interpretation, BRI. Claim 1 is directed to an “encipher core” which comprises other listed elements. Claimed non-transitory computer-readable medium is hardware, however, other claimed limitations, such as different subassemblies which include various modules that could be interpreted as both HW or SW, e.g., a module could be interpreted as a SW module, that is a non-statutory element. Note, that Fig. 8C presented on a New Sheet of Drawings clearly depicts architecture of a SW but not a HW unit.
On p. 21 applicant further asserts that “encipher core” is well-understood hardware descriptions in digital logic and integrated circuit design.
Examiner respectfully disagrees and submits, that an example of the “encipher core” as a SW could be the “Encypher Core” which is an open-source Python software package published on “PyPI”, i.e., Pyton Package Index site. This package is designed to invisibly embed and extract metadata in plain text using Unicode variation selectors (often used for tracking provenance and verifying AI-generated content).
One way to overcome the 101 rejection could be to replace “encipher core” in claim 1 for non-transitory computer-readable medium storing instruction that by execution perform different operations or to claim an apparatus comprising specified assemblies performing respective operations.
Regarding applicant’s comment on mental process on pp. 23-24 examiner respectfully submits that following steps are interpreted in the OA as a mental process: “receive a plaintext…”, “receive …a round key…”, “add the round key to the result array…”. This interpretation was in accordance with MPEP § 2106.04(a)(2), subsection III, where it examples a claim to "performing a mental process on a computer environment” as a Mental Process. Interpretation as a mental process could be avoided by focusing on description of concept essential features removing extended disclosure of standard computational steps.
On p. 25-32 of the Remarks applicant disputes rejection under 102 and 103 clarifying advantages of specific steps in data processing compared with the prior art of DR2020 also in view of Michiels. Examiner respectfully submits that optimizing an existing encryption algorithm is not the same as the development of a novel method or system indicating patentability of application. In addition, in a prior art of Johnson et al. US 9906360 the byte-wide data operations within AES are disclosed.
Applicant asserts that byte-like operation of first and second lookup tables should be considered as an original aspect of the application. It is understood that bit-wide system handles data one single bit at a time, but the byte-wide system process data in 8-bit chunks simultaneously and is beneficial for computation. However, this point alone cannot indicate patentability unless it is demonstrated to be a result of specific and original HW architecture that is missing in the claim disclosure. Instead, claims are overloaded with detailed disclosures of different encryption algorithm related operations. Key features of the algorithm and related data processing are disclosed in the prior art and amended claims do not overcome it.
Accordingly, rejection under 101 and 103 maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 2 and 5 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over J. Daemen, V. Rijmen, The Design of Rijndael. The Advanced Encryption Standard. 2d ed., Springer, 2020) (hereafter DR2020) and in view of Johnson et al. (US 9906360) (hereafter Johnson).
As per claim 1 DR2020 discloses: An encipher core, comprising:a non-transitory computer-readable medium storing a first lookup table, a second lookup table, a plaintext, and a round key (Examiner note: the lookup table is essentially equivalent to other known in the prior art terms of substitution table, substitution box, SubBytes or S-Box, see DR2020, sec. 4) (DR2020 in sec. 4.2.1 discloses structure and implementation of look-up table, SubBytes() function, a substitution box, S-box() function of AES),
the first lookup table constructed by performing a byte substitution in accordance with a SubBytes transformation conforming to requirements of an Advanced Encryption Standard followed by a multiplication in GF(28) by three modulo x4+ 1, the second lookup table constructed by performing the byte substitution in accordance with the SubBytes transformation conforming to the requirements of the Advanced Encryption Standard followed by a multiplication in GF(28) by two modulo x4 + 1 (DR2020 in sec. 4.3.2 discloses properties and applications of Galois Field, i.e., GF(28), including addition and multiplication in GF(28) using modulo of the fixed polynomials),
the plaintext being a data message to be encrypted having a plurality of bytes, the round key being a cipher key having a plurality of bytes;a ShiftRows subassembly operable to shift the bytes of the plaintext in accordance with a ShiftRows transformation conforming to the requirements of the Advanced Encryption Standard (DR2020 in sec. 3.4.2 discloses properties of ShiftRows() transformation including examples for the recited operations);
a combined SubBytes and MixColumns subassembly including four combined SubBytes and MixColumns modules, each of the combined SubBytes and MixColumns modules including: a first data conversion engine operable to convert a first portion of the plaintext into a first result using the first lookup table; (DR2020 in sec. 4.1.2 discloses combinations of transformation modules S-box, i.e., SubBytes, and MixColumns into a single logic function for optimized implementation in the AES algorithm);
a second data conversion engine operable to convert a second portion of the plaintext into a second result using the second lookup table; (DR2020 in sec. 10.2, 11.1 discloses implementation of data conversion AES modules for transformation of specified portions of a plaintext into ciphertext using byte substitution according to respective lookup table);
and a bitwise even parity checker operable to accept as operands the first result, the second result, and a third portion of the plaintext to produce a result array row (DR2020 in sec. 2.2 discloses properties and implementation of the parity-check matrix for bitwise encoding operations for respective text portions);
and an AddRoundKey subassembly operable to add the round key to the result array in accordance with an AddRoundKey transformation conforming to the requirements of the Advanced Encryption Standard to produce a ciphertext indicative of the plaintext (DR2020 in sec. 10.2.1 discloses implementation of the AddRoundKey transformation module for the data encryption addressing the recited operations),
the result array formed by the result array rows from the four combined SubBytes and MixColumns modules, wherein the combined SubBytes and MixColumns subassembly conforms to the requirements of the Advanced Encryption Standard such that the ciphertext can be reverted to the plaintext using a decipher core conforming to the requirements of the Advanced Encryption Standard (DR2020 in sec 4.1.2 discloses different combinations of four transformation modules according to the AES standard with examples for respective data encoding addressing the recited limitations).
DR2020 failed to specifically disclose: data operation at byte-wide level using AES algorithm. However, Johnson discloses (Examiner note: the underscored portion has been marked in claim posted on 07/27/2026):
in accordance with a MixColumns transformation conforming to the requirements of the Advanced Encryption Standard, the third portion comprising at least two bytes of the plaintext and having been substituted in accordance with the SubBytes transformation; (Johnson, in col. 53, ll. 64-67 discloses MixColumns transformation operating at byte-wide level within the AES algorithm).
It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention to modify DR2020, in view of teaching of Johnson because they both disclose data encoding using the AES algorithm. The motivation to combine would be to modify DR2020 for teaching of Johnson for operating at byte-wide level by different transformation modules disclosed by DR2020 in order to improve efficiency of the AES method.
As per claim 2 DR2020 as modified by Johnson discloses: The encipher core of claim 1, wherein the first lookup table has 256 first values, each of the 256 first values having one byte, and the second lookup table has 256 second values, each of the 256 second values having one byte (Examiner note: claim 2 repeats a definition of a look-up table, for the AES-256 format as disclosed by DR2020 in secs. 4, 4.1.2, 4.2.1 and 4.3).
As per claim 5 DR2020 as modified by Johnson discloses: The encipher core of claim 1, wherein the plaintext has 16 bytes arranged into four plaintext rows including a first plaintext row, a second plaintext row, a third plaintext row, and a fourth plaintext row, each of the plaintext rows having four bytes, and the round key has 16 bytes. (DR2020 in secs.4.2, 5.3.3, Application B discloses structure of 16-bytes values, respective matrix constructions for encryption/decryption operations).
As per claim 6 DR2020 as modified by Johnson discloses: The encipher core of claim 5, wherein the ShiftRows subassembly is operable to shift the bytes of the plaintext such that the first plaintext row is shifted by zero bytes, the second plaintext row is shifted by one byte, the third plaintext row is shifted by two bytes, and the fourth plaintext row is shifted by three bytes. (DR2020 in sec. 3.4 discloses structure, properties and implementation of the ShitRows function addressing recited limitations).
As per claim 7 DR2020 as modified by Johnson discloses: The encipher core of claim 5, wherein the combined SubBytes and MixColumns modules include a first combined SubBytes and MixColumns module, a second combined SubBytes and MixColumns module, a third combined SubBytes and MixColumns module, and a fourth combined SubBytes and MixColumns module, (DR2020 in sec. 3.4.4, 4.1.2 discloses different combinations of recited transformation modules into a single logic function for optimized implementation in the AES algorithm);
wherein: the first portion of the plaintext operated on by the first combined SubBytes and MixColumns module is the third plaintext row;the second portion of the plaintext operated on by the first combined SubBytes and MixColumns module is the [[third]] fourth plaintext row;the third portion of the plaintext operated on by the first combined SubBytes and MixColumns module includes the first plaintext row and the second plaintext row (DR2020 discloses in sec. 4.1.2 rows and columns of respective data matrices transformations related to the combinations of MixColumns functions with others transformation functions addressing recited operations);
the first portion of the plaintext operated on by the second combined SubBytes and MixColumns module is the [[third]] second plaintext row;the second portion of the plaintext operated on by the second combined SubBytes and MixColumns module is the third plaintext row; the third portion of the plaintext operated on by the second combined SubBytes and MixColumns module includes the first plaintext row and the fourth plaintext row; the first portion of the plaintext operated on by the third combined SubBytes and MixColumns module is the first plaintext row; the second portion of the plaintext operated on by the third combined SubBytes and MixColumns module is the [[first]] second plaintext row; the third portion of the plaintext operated on by the third combined SubBytes and MixColumns module includes the third plaintext row and the fourth plaintext row; the first portion of the plaintext operated on by the fourth combined SubBytes and MixColumns module is the [[first]] fourth plaintext row; the second portion of the plaintext operated on by the fourth combined SubBytes and MixColumns module is the second plaintext row and the third plaintext row (DR2020 in sec. 3.4 discloses round transformations of respective matrices demonstrating row-by row transformations of plaintext data related to respective combinations of the transformation functions by encryption, sec. 4.1.2, or decryption, sec. 4.1.3 addressing listed details of the data transformation as examples).
As per claim 8 DR2020 discloses: A non-transitory computer readable medium having software instructions stored thereon that, when executed by a processor, cause the processor to:receive a plaintext and a round key, the plaintext being a data message to be encrypted having a plurality of bytes, the round key being an encryption key having a plurality of bytes (DR2020 discloses in sec. 2.4 a cipher key for encryption of a plaintext);
shift the bytes of the plaintext in accordance with a ShiftRows transformation conforming to requirements of an Advanced Encryption Standard; (DR2020 in sec. 3.4.2 discloses properties and application of ShiftRows() transformation according to the Advanced Encryption Standard);
populate four result array rows of a result array, wherein populating a result array row of the four result array rows includes: converting a first portion of the plaintext into a first result using a first lookup table, the first lookup table constructed by performing a byte substitution in accordance with a SubBytes transformation conforming to the requirements of an Advanced Encryption Standard, (DR2020 in sec. 4.2.1 discloses structure and implementation of look-up table, SubBytes() function, a substitution box, S-box() function of AES),
followed by a multiplication in GF(28) by three modulo x4 + 1; converting a second portion of the plaintext into a second result using a second lookup table, the second lookup table constructed by performing a byte substitution in accordance with the SubBytes transformation, followed by a multiplication in GF(28) by two modulo x4 + 1; (DR2020 in sec. 4.3.2 discloses properties and applications of Galois Field, i.e., GF(28), including addition and multiplication in GF(28) using modulo of the fixed polynomials);
and performing a bitwise even parity check, using as operands the first result, the second result, and a third portion of the plaintext to produce the result array row (DR2020 in sec. 2.2 discloses properties and implementation of the parity-check matrix for bitwise encoding operations for respective text portions);
and add the round key to the result array in accordance with an AddRoundKey transformation conforming to the requirements of the Advanced Encryption Standard to produce a ciphertext indicative of the plaintext, (DR2020 in sec. 10.2.1 discloses implementation of the AddRoundKey transformation module for the data encryption addressing the recited operations),
wherein the step of populating the four result array rows of the result array using the plaintext conforms to the requirements of the Advanced Encryption Standard such that the ciphertext can be reverted to the plaintext using a decipher core conforming to the requirements of the Advanced Encryption Standard (DR2020 discloses in sec. 3 decryption within the Advanced Encryption Standard reverting the encoded data into the plaintext).
DR2020 failed to specifically disclose: data operation at byte-wide level using AES algorithm. However, Johnson discloses (Examiner note: the underscored portion has been marked in claim posted on 07/27/2026):
in accordance with a MixColumns transformation conforming to the requirements of the Advanced Encryption Standard, the third portion comprising at least two bytes of the plaintext and having been substituted in accordance with the SubBytes transformation; (Johnson, in col. 53, ll. 64-67 discloses MixColumns transformation operating at byte-wide level within the AES algorithm).
It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention to modify DR2020, in view of teaching of Johnson because they both disclose data encoding using the AES algorithm. The motivation to combine would be to modify DR2020 for teaching of Johnson for operating at byte-wide level by different transformation modules disclosed by DR2020 in order to improve efficiency of the AES method.
As per claims 9, 10 and 11, claims 9, 10 and 11 encompass same or similar scope as claims 2, 5 and 6, respectively. Therefore, claims 9, 10 and 11 are rejected based on the same reasons set forth above in rejecting claims 2, 5 and 6.
As per claim 12, claim 12 encompasses same or similar scope as claim 8. Therefore, claim 12 is rejected based on the same reasons set forth above in rejecting claim 8.
As per claims 13, 14 and 15, claims 13, 14 and 15 encompass same or similar scope as claims 2, 5 and 6, respectively. Therefore, claims 3, 14 and 15 are rejected based on the same reasons set forth above in rejecting claims 2, 5 and 6.
As per claim 16 DR2020 as modified by Johnson discloses: The method of claim 12, wherein the round key is a first round key of a plurality of round keys, each of the plurality of round keys together constituting a key schedule (DR2020 discloses in sec. 3.4.4 generation of an array of round keys derived from the cipher key by combined transformation AddRoundKey and XOR thus creating a key schedule disclosed by DR2020 in sec. 3.6).
As per claim 17 DR2020 as modified by Johnson discloses: The method of claim 16, wherein the steps of the method are repeated using a new round key of the plurality of round keys until each of the plurality of round keys of the key schedule has been used (DR2020 discloses in sec. 3.6 step by step creation of the key schedule by key expansion and round key selection process).
Claims 3 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over J. Daemen, V. Rijmen, The Design of Rijndael. The Advanced Encryption Standard. 2d ed., Springer, 2020) (hereafter DR2020), and in view of Johnson et al. (US 9906360) (hereafter Johnson), and in view of Michiels et al. (US 20160267258) (hereafter Michiels).
As per claim 3 DR2020 as modified by Johnson failed to specifically disclose: implementation of the finite state machine by using the AES algorithm.
However, Michiels discloses: The encipher core of claim 1, further comprising a finite state machine having a plurality of predetermined states including: a ShiftRows state, wherein the ShiftRows subassembly is operated to shift the bytes of the plaintext in accordance with the ShiftRows transformation; a combined SubBytes and MixColumns state, wherein the combined SubBytes and MixColumns subassembly is operated to produce the result array; and an AddRoundKey state, wherein the AddRoundKey subassembly is operated to add the round key to the result array in accordance with the AddRoundKey transformation to produce the ciphertext, wherein the finite state machine is operable to transition between the plurality of predetermined states in response to detection of a trigger event. (Michiels, in para. [0028-0029] discloses the finite state machine for encryption by using a white-box implementation with the AES encryption algorithm).
It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention to modify DR2020-Johnson, in view of teaching of Michiels because they all disclose data encoding using the AES algorithm. The motivation to combine would be to modify DR2020-Johnson for teaching of Michiels for implementing the finite state machine with combinations of different transformation modules disclosed by DR2020 into a data transformation function in order to improve efficiency of the AES method.
As per claim 4 DR2020 as modified by Johnson and Michiels discloses: The encipher core of claim 3, wherein the trigger event is indicative of the completion of a transformation by one of the ShiftRows subassembly, the combined SubBytes and MixColumns subassembly, and the AddRoundKey subassembly. (Michiels, in para. [0032,0042] discloses introduction of a specified numbers into transformation functions that are indicators of completion of the transformation, i.e., event trigger).
It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention to modify DR2020-Johnson, in view of teaching of Michiels because they all disclose data encoding using the AES algorithm. The motivation to combine would be to modify DR2020-Johnson for teaching of Michiels for implementing the finite state machine with combinations of different transformation modules disclosed by DR2020 into a data transformation function in order to improve efficiency of the AES method.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VLADIMIR IVANOVICH GAVRILENKO whose telephone number is (313) 446-6530. The examiner can normally be reached on Monday-Friday 7:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynn Feild can be reached on (571) 272-2092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Vladimir I. Gavrilenko/Examiner, Art Unit 2431
/LYNN D FEILD/Supervisory Patent Examiner, Art Unit 2431
