DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Obligation Under 37 CFR 1.56 – Joint Inventors
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Status of Claims
Claims 1-14 are pending in this application, with non-elected claims 10-12 withdrawn from consideration. Thus, claims 1-9 and 13-14 are still under consideration, with claim 1 being independent.
Election/Restrictions
Applicant’s election of Species I (claims 1-9 and 13-14), with traverse, in the reply filed on April 9, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings were received on September 26, 2024. These drawings are acceptable.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art;
Ascertaining the differences between the prior art and the claims at issue;
Resolving the level of ordinary skill in the pertinent art; and
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 7-9 and 13-14 are rejected under 35 U.S.C. 103 as being obvious over MORINO et al. (US 20120036418 A1, hereinafter “MORINO”).
Regarding claim 1, MORINO discloses a circuit device (FIG. 6: “DISPLAY OUTPUT CONTROL UNIT” 100) comprising:
an overlay processing circuit (¶ [0049]: “overlay control unit 105”; See FIG. 2 and FIG. 6.) that performs overlay processing (¶ [0049]: “The overlay control unit 105 has a function of overlaying the image data transferred by the plane-1 control unit 108-1, the plane-2 control unit 108-2, and the plane-n control unit 108-n.”) of first input image data (e.g., ¶ [0049]: “the image data transferred by the plane-1 control unit 108-1,” See hypothetical “1st input image data” in the drawing(s) herein below.) on a first area (See hypothetical “1st area” in “2nd input image data” in the drawing(s) herein below.) of second input image data (¶ [0049]: “the image data transferred by” … “the plane-2 control unit 108-2,” See hypothetical “2nd input image data” in the drawing(s) herein below.) and outputs a result of the overlay processing as output image data (¶ [0036]: “forms image data to be displayed by overlaying the image data received by the plane control unit.” ¶ [0049]: “The overlay control unit 105 has a function of overlaying the image data transferred by the plane-1 control unit 108-1, the plane-2 control unit 108-2, and the plane-n control unit 108-n. The image quality adjustment unit 107 adjusts the quality of the image output from the overlay control unit 105. The image data whose quality has been adjusted by the image quality adjustment unit 107 is transmitted to the display unit 30 for display.” ¶ [0049]: “The comparison control unit 106 receives the output of the plane-2 control unit 108-2 and the plane-n control unit 108-n or the output of the overlay control unit 105, and performs a cyclic redundancy check over an arbitrary region of the image data.” ¶ [0052]: “transmits overlaid image information from the overlay control unit 105,” NOTE: See hypothetical “Output image data” in the drawing(s) provided herein below, wherein a 1st input image is overlayed on a 1st area of a 2nd input image such that the overlayed output image includes the 1st image in the 1st area and the part of the 2nd input image in a 2nd area of the 2nd input image.) (¶ [0036]: “the display output control unit further comprises a plurality of plane control units (108-1, 108-2 . . . and 108-n) for receiving different image data respectively, and an overlay control unit (105) which forms image data to be displayed by overlaying the image data received by the plane control unit.” ¶ [0049]: “The overlay control unit 105 has a function of overlaying the image data transferred by the plane-1 control unit 108-1, the plane-2 control unit 108-2, and the plane-n control unit 108-n.”); and
an error detection circuit (FIG. 6; “COMPARISON CONTROL UNIT” 106a,106b,106c, …, 106n. ¶ [0034]: “a comparison control unit (106) which performs a cyclic redundancy check over an arbitrary region of the image data displayed on the display unit.” ¶ [0050]: “FIG. 1 illustrates an exemplary configuration of the comparison control unit 106.”) that calculates a first error code value (¶ [0034]: “the result of the arithmetic processing” ¶ [0052]: “The CRC arithmetic processing unit 122 performs CRC arithmetic processing of the image data transmitted via the selector 121. The CRC arithmetic processing by the CRC arithmetic processing unit 122 is performed over a region selected by the region control unit 125. The region control unit 125 performs region control on the image information based on comparison region information.”) corresponding to image data of the first area of the output image data (¶ [0034]: “a region of the image data based on comparison region information for specifying an arbitrary region of the image” ¶ [0034]: “as a cyclic redundancy check target region,” NOTE: The cyclic redundancy check target region is arbitrarily selected. Thus, a first region for error detection could obviously be the 1st area in the output image data of the hypothetical scenario shown in the drawing herein below.) and a second error code value (¶ [0034]: “the result of the arithmetic processing” ¶ [0052]: “The CRC arithmetic processing unit 122 performs CRC arithmetic processing of the image data transmitted via the selector 121. The CRC arithmetic processing by the CRC arithmetic processing unit 122 is performed over a region selected by the region control unit 125. The region control unit 125 performs region control on the image information based on comparison region information.”) corresponding to image data of a second area not overlapping the first area of the output image data (e.g., such as the 2nd area in the output image data shown in the drawing provided below.) (¶ [0034]: “The comparison control unit includes a region control unit (125) which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit (122) which performs arithmetic processing for the cyclic redundancy check over a region selected by the region control unit, and a comparison circuit (123) which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value.” ¶ [0037]: “a plurality of the comparison control units can be provided, the comparison control units performing, in parallel, the cyclic redundancy check over an arbitrary region of the image data respectively displayed on the display unit. Accordingly, the cyclic redundancy check on a plurality of regions can be immediately performed.” ¶ [0052]: “The region control unit 125 performs region control on the image information based on comparison region information. With the region control on the image information, a data enable signal for the CRC arithmetic processing unit 122 is asserted by the region control unit 125 at the timing when image information corresponding to the comparison region is input to the CRC arithmetic processing unit 122. For example, the region control unit 125 includes a first counter which counts the number of scanning lines of the display frame and a second counter which counts the horizontal dot clock, determines whether or not the output of the selector 121 falls within the comparison region based on the count values of the first counter and the second counter and, if the output of the selector 121 falls within the comparison region, asserts a data enable signal. The CRC arithmetic processing unit 122 calculates the CRC of the input image data at the timing when the data enable signal is asserted. The CRC for the comparison region is obtained by such arithmetic processing. In addition, the falling edge timing of a vertical synchronizing signal 135 transmitted from the overlay control unit 105 is detected by the region control unit 125. The falling edge timing of the vertical synchronizing signal 135 is transmitted from the region control unit 125 to the comparison circuit 123 and the interrupt control circuit 124. The operation information register 126 has a value indicating whether or not to operate the comparison control unit 106 stored therein. If a value indicating an operation is stored, an enable signal to be output to the region control unit 125 is asserted. Asserting the enable signal starts operating the region control unit 125. The comparison region information is held in the comparison region information registers 128. The comparison region information held in the comparison region information registers 128 includes information for specifying the comparison region such as a start position X (131) of the comparison region, a start position Y (132) of the comparison region, a size X (133) of the comparison region, and a size Y (134) of the comparison region, for example. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value (also referred to as "CRC expected value"). The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129. The result of CRC computation is transmitted to the subsequent comparison circuit 123. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value in synchronization with the falling edge timing of the vertical synchronizing signal 135. The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129.”),
and performs error detection on the output image data (¶ [0034]: “performs error detection”) by comparing (¶ [0034]: “performs error detection by comparing) the first error code value (e.g., ¶ [0034]: “the result of the arithmetic processing”) with a first expected value (e.g., ¶ [0034]: “with its expected value.” ¶ [0051]: “a CRC expected value”) which is an expected value of the first error code value (¶ [0034]: “performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value.”) and comparing the second error code value with a second expected value which is an expected value of the second error code value ( ) (¶ [0034]: “The comparison control unit includes a region control unit (125) which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit (122) which performs arithmetic processing for the cyclic redundancy check over a region selected by the region control unit, and a comparison circuit (123) which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value.” ¶ [0035]: “arithmetic processing for cyclic redundancy check is performed over the selected region by selecting a region of the image data based on the comparison region information for specifying an arbitrary region of the image displayed on the display unit as a target region of the cyclic redundancy check. Error detection by the cyclic redundancy check is performed only on the target region of the cyclic redundancy check, and thus it suffices to prepare as many expected values of the arithmetic processing result for the cyclic redundancy check as the number of states of the cyclic redundancy check target region (comparison region). It thus prevents the amount of data of the expected value from being overwhelming, and whereby the cyclic redundancy check can be easily implemented. Accordingly, a graphic display instrument panel can appropriately check whether or not data display is normal.” ¶[0037]: “a plurality of the comparison control units can be provided, the comparison control units performing, in parallel, the cyclic redundancy check over an arbitrary region of the image data respectively displayed on the display unit. Accordingly, the cyclic redundancy check on a plurality of regions can be immediately performed.” ¶ [0052]: “The region control unit 125 performs region control on the image information based on comparison region information. With the region control on the image information, a data enable signal for the CRC arithmetic processing unit 122 is asserted by the region control unit 125 at the timing when image information corresponding to the comparison region is input to the CRC arithmetic processing unit 122. For example, the region control unit 125 includes a first counter which counts the number of scanning lines of the display frame and a second counter which counts the horizontal dot clock, determines whether or not the output of the selector 121 falls within the comparison region based on the count values of the first counter and the second counter and, if the output of the selector 121 falls within the comparison region, asserts a data enable signal. The CRC arithmetic processing unit 122 calculates the CRC of the input image data at the timing when the data enable signal is asserted. The CRC for the comparison region is obtained by such arithmetic processing. In addition, the falling edge timing of a vertical synchronizing signal 135 transmitted from the overlay control unit 105 is detected by the region control unit 125. The falling edge timing of the vertical synchronizing signal 135 is transmitted from the region control unit 125 to the comparison circuit 123 and the interrupt control circuit 124. The operation information register 126 has a value indicating whether or not to operate the comparison control unit 106 stored therein. If a value indicating an operation is stored, an enable signal to be output to the region control unit 125 is asserted. Asserting the enable signal starts operating the region control unit 125. The comparison region information is held in the comparison region information registers 128. The comparison region information held in the comparison region information registers 128 includes information for specifying the comparison region such as a start position X (131) of the comparison region, a start position Y (132) of the comparison region, a size X (133) of the comparison region, and a size Y (134) of the comparison region, for example. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value (also referred to as "CRC expected value"). The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129. The result of CRC computation is transmitted to the subsequent comparison circuit 123. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value in synchronization with the falling edge timing of the vertical synchronizing signal 135. The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129.” ¶ [0064]: “The display control apparatus 1 shown in FIG. 6 substantially differs from that shown in FIG. 2 in that the cyclic redundancy check can be performed over a plurality of regions simultaneously because a plurality of comparison control units denoted by reference numerals 106a to 106n is provided,” ¶ [0065]: “Because the comparison control units 106a to 106n are provided in this example, the comparison control unit 106a may perform CRC error detection for the plane-1, the comparison control unit 106b may perform. CRC error detection for the plane-2, the comparison control unit 106c may perform CRC error detection for the plane 3, and the comparison control unit 106n may perform CRC error detection for the plane-n. Therefore, the cyclic redundancy check can be performed simultaneously over a plurality of regions.” NOTE: Thus, with the display output control unit 100 shown in FIG. 6, multiple comparison control units 106a-106n enable error detection for multiple different arbitrary regions of the overlaid image data output from the overlay control unit 105, e.g., such as for the 1st area and the 2nd area in the output image data shown in the drawing below. As shown in FIG. 1, each comparison control unit 106a-106n in FIG. 6 can also perform error detection on the arbitrary regions of the image data output from the overlay control unit 105 Thus, for the display control apparatus of FIG. 6, and using two separate comparison control units (e.g., see comparison control unit 106 in FIG. 1), the output image from the overlay control unit (e.g., such as the output image data in the drawing provided below) can be error tested for both the 1st area comprising 1st input image data and the 2nd area comprising the second input image data not overlapped by the superimposed 1st input image data.).
[AltContent: rect][AltContent: rect][AltContent: rect][AltContent: textbox (1st input image data)][AltContent: rect][AltContent: textbox (Output image data with 1st input image overlaid on the 1st area of the 2nd input image.)][AltContent: rect][AltContent: textbox (2nd input image data)]
[AltContent: arrow][AltContent: arrow] 1st area 1st area
[AltContent: arrow][AltContent: arrow]
2nd area 2nd area
Drawing: Hypothetical 1st and 2nd images input to overlay processing circuit and the resulting output image data after the 1st input image data is superimposed onto the 1st area of the 2nd input image data.. Note that the 2nd area in the output image data (which is the same as the 2nd area in the 2nd input image data) does not overlap the 1st area of the output image data (which is the same as the 1st area of the 2nd input image data).
[AltContent: textbox ()]
Thus, as simply a matter of design choice (e.g., a choice of input images to be overlaid, a choice of how the input images are overlaid, and a choice of the areas of the overlaid image data to subjected to error detection), one of ordinary skill in the art would understand that the circuit device disclosed by MORINO (e.g., the display control apparatus shown in FIG. 6 including a plurality of the comparison control units 106 shown in FIG. 1) is clearly capable of functioning the same as the claimed invention.
Regarding claim 3 (depends on claim 1), MORINO further teaches, and/or renders obvious:
wherein the error detection circuit (FIG. 6; “COMPARISON CONTROL UNIT” 106a,106b,106c, …, 106n. ¶ [0034]: “a comparison control unit (106) which performs a cyclic redundancy check over an arbitrary region of the image data displayed on the display unit.” ¶ [0050]: “FIG. 1 illustrates an exemplary configuration of the comparison control unit 106.”) calculates the second error code value from the image data of the second area excluding the image data of the first area from the output image data (¶ [0052]: “The region control unit 125 performs region control on the image information based on comparison region information. With the region control on the image information, a data enable signal for the CRC arithmetic processing unit 122 is asserted by the region control unit 125 at the timing when image information corresponding to the comparison region is input to the CRC arithmetic processing unit 122.” ¶ [0052]: “The CRC arithmetic processing unit 122 calculates the CRC of the input image data at the timing when the data enable signal is asserted. The CRC for the comparison region is obtained by such arithmetic processing.” ¶ [0064]: “The display control apparatus 1 shown in FIG. 6 substantially differs from that shown in FIG. 2 in that the cyclic redundancy check can be performed over a plurality of regions simultaneously because a plurality of comparison control units denoted by reference numerals 106a to 106n is provided,” NOTE: In the hypothetical instance of 1st input imaged data overlaid onto the 1st area of the 2nd input image data to produce the output image data shown in the drawing provided herein-above, the CRC value for the 2nd area in the output image data can be calculated only for the 2nd area, thereby excluding the image data of the 1st area in the output image data from being used to calculate the CRC value for the 2nd area in the output image data. In other words, if the 2nd area in the output image data is set as a comparison region in the region control unit 125 of a 2nd of the comparison control units 106a to 106n, the CRC arithmetic processing unit 122 calculates the CRC only for the 2nd area of the output image data, excluding the 1st area of the output image data.).
Regarding claim 4 (depends on claim 1), MORINO further teaches, and/or renders obvious:
wherein the error detection circuit (i.e., the plurality of comparison control units 106a-106n in FIG. 6, which are shown in detail in FIG. 1) includes an error-detection-area determination circuit (e.g., the region control units 125 and comparison region information registers 128 (as shown in FIG. 1) included in each of the comparison control units 106a-106n in FIG. 6) that determines whether each pixel of the output image data belongs to the first area or the second area (As is clear shown in the combination of FIG. 1 and FIG. 6, for each of the comparison control units 106a-106n in FIG. 6 (each of which corresponds to the comparison control unit 106 in FIG. 1), the respective region control units 125a-125n in combination with respective comparison region information registers 128a -128n (i.e., region control unit 125 and comparison region information registers 128 shown in FIG. 1). NOTE: For the hypothetical output image data having 1st and 2nd areas shown in the drawing provided herein-above in the rejection of claim 1, only two comparison control units would be required, i.e., 106a and 106b, for respectively error checking the 1st area and the 2nd area in the overlaid output image data. In other words, the information in the comparison region information registers 128 in a first comparison control unit 106a would be set to check pixels in the 1st area of the output image data, and the information in the comparison region information registers 128 in a second comparison control unit 106b would be set to check pixels in the 2nd area of the output image data.),
a first-area error determination circuit (e.g., CRC arithmetic processing unit 122, comparison circuit 123 and CRC expected value information register 129 (shown in FIG. 1) included in a first of the comparison control units 106a-106n in FIG. 6) that calculates the first error code value for a pixel determined to belong to the first area (e.g., a first CRC value calculated by CRC arithmetic processing unit 122 for the 1st area of the output image data in the hypothetical image data example shown in the drawing provided herein-above in the rejection of claim 1) and compares the first error code value with the first expected value (¶ [0034]: “The display output control unit (100) includes a comparison control unit (106) which performs a cyclic redundancy check over an arbitrary region of the image data displayed on the display unit. The comparison control unit includes a region control unit (125) which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit (122) which performs arithmetic processing for the cyclic redundancy check over a region selected by the region control unit, and a comparison circuit (123) which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value.” ¶ [0035]: “According to the above configuration, arithmetic processing for cyclic redundancy check is performed over the selected region by selecting a region of the image data based on the comparison region information for specifying an arbitrary region of the image displayed on the display unit as a target region of the cyclic redundancy check. Error detection by the cyclic redundancy check is performed only on the target region of the cyclic redundancy check,” ¶ [0052]: “The CRC arithmetic processing unit 122 performs CRC arithmetic processing of the image data transmitted via the selector 121. The CRC arithmetic processing by the CRC arithmetic processing unit 122 is performed over a region selected by the region control unit 125. The region control unit 125 performs region control on the image information based on comparison region information. With the region control on the image information, a data enable signal for the CRC arithmetic processing unit 122 is asserted by the region control unit 125 at the timing when image information corresponding to the comparison region is input to the CRC arithmetic processing unit 122. For example, the region control unit 125 includes a first counter which counts the number of scanning lines of the display frame and a second counter which counts the horizontal dot clock, determines whether or not the output of the selector 121 falls within the comparison region based on the count values of the first counter and the second counter and, if the output of the selector 121 falls within the comparison region, asserts a data enable signal. The CRC arithmetic processing unit 122 calculates the CRC of the input image data at the timing when the data enable signal is asserted. The CRC for the comparison region is obtained by such arithmetic processing. In addition, the falling edge timing of a vertical synchronizing signal 135 transmitted from the overlay control unit 105 is detected by the region control unit 125. The falling edge timing of the vertical synchronizing signal 135 is transmitted from the region control unit 125 to the comparison circuit 123 and the interrupt control circuit 124. The operation information register 126 has a value indicating whether or not to operate the comparison control unit 106 stored therein. If a value indicating an operation is stored, an enable signal to be output to the region control unit 125 is asserted. Asserting the enable signal starts operating the region control unit 125. The comparison region information is held in the comparison region information registers 128. The comparison region information held in the comparison region information registers 128 includes information for specifying the comparison region such as a start position X (131) of the comparison region, a start position Y (132) of the comparison region, a size X (133) of the comparison region, and a size Y (134) of the comparison region, for example. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value (also referred to as "CRC expected value"). The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129. The result of CRC computation is transmitted to the subsequent comparison circuit 123. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value in synchronization with the falling edge timing of the vertical synchronizing signal 135. The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129. If the result of the arithmetic processing by the CRC arithmetic processing unit 122 and its expected value do not match, an error signal is asserted from the comparison circuit 123 to the interrupt control circuit 124.” ¶ [0064]: “The display control apparatus 1 shown in FIG. 6 substantially differs from that shown in FIG. 2 in that the cyclic redundancy check can be performed over a plurality of regions simultaneously because a plurality of comparison control units denoted by reference numerals 106a to 106n is provided,”), and
a second-area error determination circuit (e.g., CRC arithmetic processing unit 122, comparison circuit 123 and CRC expected value information register 129 (shown in FIG. 1) included in a second of the comparison control units 106a-106n in FIG. 6) that calculates the second error code value for a pixel determined to belong to the second area (e.g., a second CRC value calculated by CRC arithmetic processing unit 122 for the 2nd area of the output image data in the hypothetical image data example shown in the drawing provided herein-above in the rejection of claim 1) and compares the second error code value with the second expected value (¶ [0034]: “The display output control unit (100) includes a comparison control unit (106) which performs a cyclic redundancy check over an arbitrary region of the image data displayed on the display unit. The comparison control unit includes a region control unit (125) which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit (122) which performs arithmetic processing for the cyclic redundancy check over a region selected by the region control unit, and a comparison circuit (123) which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value.” ¶ [0035]: “According to the above configuration, arithmetic processing for cyclic redundancy check is performed over the selected region by selecting a region of the image data based on the comparison region information for specifying an arbitrary region of the image displayed on the display unit as a target region of the cyclic redundancy check. Error detection by the cyclic redundancy check is performed only on the target region of the cyclic redundancy check,” ¶ [0052]: “The CRC arithmetic processing unit 122 performs CRC arithmetic processing of the image data transmitted via the selector 121. The CRC arithmetic processing by the CRC arithmetic processing unit 122 is performed over a region selected by the region control unit 125. The region control unit 125 performs region control on the image information based on comparison region information. With the region control on the image information, a data enable signal for the CRC arithmetic processing unit 122 is asserted by the region control unit 125 at the timing when image information corresponding to the comparison region is input to the CRC arithmetic processing unit 122. For example, the region control unit 125 includes a first counter which counts the number of scanning lines of the display frame and a second counter which counts the horizontal dot clock, determines whether or not the output of the selector 121 falls within the comparison region based on the count values of the first counter and the second counter and, if the output of the selector 121 falls within the comparison region, asserts a data enable signal. The CRC arithmetic processing unit 122 calculates the CRC of the input image data at the timing when the data enable signal is asserted. The CRC for the comparison region is obtained by such arithmetic processing. In addition, the falling edge timing of a vertical synchronizing signal 135 transmitted from the overlay control unit 105 is detected by the region control unit 125. The falling edge timing of the vertical synchronizing signal 135 is transmitted from the region control unit 125 to the comparison circuit 123 and the interrupt control circuit 124. The operation information register 126 has a value indicating whether or not to operate the comparison control unit 106 stored therein. If a value indicating an operation is stored, an enable signal to be output to the region control unit 125 is asserted. Asserting the enable signal starts operating the region control unit 125. The comparison region information is held in the comparison region information registers 128. The comparison region information held in the comparison region information registers 128 includes information for specifying the comparison region such as a start position X (131) of the comparison region, a start position Y (132) of the comparison region, a size X (133) of the comparison region, and a size Y (134) of the comparison region, for example. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value (also referred to as "CRC expected value"). The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129. The result of CRC computation is transmitted to the subsequent comparison circuit 123. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value in synchronization with the falling edge timing of the vertical synchronizing signal 135. The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129. If the result of the arithmetic processing by the CRC arithmetic processing unit 122 and its expected value do not match, an error signal is asserted from the comparison circuit 123 to the interrupt control circuit 124.” ¶ [0064]: “The display control apparatus 1 shown in FIG. 6 substantially differs from that shown in FIG. 2 in that the cyclic redundancy check can be performed over a plurality of regions simultaneously because a plurality of comparison control units denoted by reference numerals 106a to 106n is provided,”).
Regarding claim 5 (depends on claim 4), MORINO further teaches, and/or renders obvious:
wherein the error-detection-area determination circuit determines, based on coordinate information of the first area, whether each pixel of the output image data belongs to the first area or the second area (¶ [0052]: “The CRC arithmetic processing unit 122 performs CRC arithmetic processing of the image data transmitted via the selector 121. The CRC arithmetic processing by the CRC arithmetic processing unit 122 is performed over a region selected by the region control unit 125. The region control unit 125 performs region control on the image information based on comparison region information. With the region control on the image information, a data enable signal for the CRC arithmetic processing unit 122 is asserted by the region control unit 125 at the timing when image information corresponding to the comparison region is input to the CRC arithmetic processing unit 122. For example, the region control unit 125 includes a first counter which counts the number of scanning lines of the display frame and a second counter which counts the horizontal dot clock, determines whether or not the output of the selector 121 falls within the comparison region based on the count values of the first counter and the second counter and, if the output of the selector 121 falls within the comparison region, asserts a data enable signal. The CRC arithmetic processing unit 122 calculates the CRC of the input image data at the timing when the data enable signal is asserted. The CRC for the comparison region is obtained by such arithmetic processing. In addition, the falling edge timing of a vertical synchronizing signal 135 transmitted from the overlay control unit 105 is detected by the region control unit 125. The falling edge timing of the vertical synchronizing signal 135 is transmitted from the region control unit 125 to the comparison circuit 123 and the interrupt control circuit 124. The operation information register 126 has a value indicating whether or not to operate the comparison control unit 106 stored therein. If a value indicating an operation is stored, an enable signal to be output to the region control unit 125 is asserted. Asserting the enable signal starts operating the region control unit 125. The comparison region information is held in the comparison region information registers 128. The comparison region information held in the comparison region information registers 128 includes information for specifying the comparison region such as a start position X (131) of the comparison region, a start position Y (132) of the comparison region, a size X (133) of the comparison region, and a size Y (134) of the comparison region, for example. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value (also referred to as "CRC expected value"). The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129. The result of CRC computation is transmitted to the subsequent comparison circuit 123. The comparison circuit 123 performs error detection by comparing the result of the arithmetic processing by the CRC arithmetic processing unit 122 with its expected value in synchronization with the falling edge timing of the vertical synchronizing signal 135. The expected value of the result of the arithmetic processing by the CRC arithmetic processing unit 122 is held in the CRC expected value information register 129. If the result of the arithmetic processing by the CRC arithmetic processing unit 122 and its expected value do not match, an error signal is asserted from the comparison circuit 123 to the interrupt control circuit 124.” NOTE: One of ordinary skill of the art would obviously understand that a first comparison control unit 106a-106n could be set to be enabled for error detection for an arbitrarily chosen first target region of the overlaid output image data, while a second comparison control unit 106a-106n could be easily modified by simply adding an inverter such that, setting the first target region, would cause the enabling signal only be active for the portion of the output image data excluding the first target region, e.g., a second target region of the output image data that excludes the first target region, in other words, the inverse of the first target region of the output image data.).
Regarding claim 7 (depends on claim 1), MORINO further teaches, and/or renders obvious:
an interface circuit (FIG. 6: “BUS I/F CONTROL UNIT” 101) that externally receives (As shown in FIG. 6, BUS I/F CONTROL UNIT 101 connects the DISPLAY OUTPUT CONTROL UNIT 100 to the circuitry of the display control apparatus 1 that is external to the DISPLAY CONTROL UNIT 100. Thus, data from the CPU 10, GRAPHIC GENERATING UNIT 14, ROM 17 and/or RAM 13 is “externally received” by the BUS I/F CONTROL UNIT 101 of the DISPLAY OUTPUT CONTROL UNIT 100.) the first input image data (such as, e.g., ¶ [0065]: “plane-1”, but using the hypothetical 1st input image shown in the drawing provided herein-above. ¶ [0054]: “image data to be displayed is read from the ROM 17 and transmitted to the image output control unit 100,” ¶ [0056]: “Display data is generated in the RAM 13 (S101) by the CPU 10 or the graphic generating unit 14.”), the second input image data (such as, e.g., ¶ [0065]: “plane-2”, but using the hypothetical 2nd input image shown in the drawing provided herein-above. ¶ [0054]: “image data to be displayed is read from the ROM 17 and transmitted to the image output control unit 100,” ¶ [0056]: “Display data is generated in the RAM 13 (S101) by the CPU 10 or the graphic generating unit 14.”), the first expected value (¶ [0054]: “CRC expected values for images corresponding to the comparison region are preliminarily calculated and stored in the ROM 17 as a table or the like in association with the image to be compared.” NOTE: As shown in FIG. 6, ROM 17 is external to the DISPLAY OUTPUT CONTROL UNIT 100. ¶ [0054]: “When the image data to be displayed is read from the ROM 17 and transmitted to the image output control unit 100, the CRC expected value for the image corresponding to the comparison region is read from the table in the ROM 17 and written in the CRC expected value information register 129.”), and the second expected value (¶ [0054]: “CRC expected values for images corresponding to the comparison region are preliminarily calculated and stored in the ROM 17 as a table or the like in association with the image to be compared.” NOTE: As shown in FIG. 6, ROM 17 is external to the DISPLAY OUTPUT CONTROL UNIT 100. ¶ [0054]: “When the image data to be displayed is read from the ROM 17 and transmitted to the image output control unit 100, the CRC expected value for the image corresponding to the comparison region is read from the table in the ROM 17 and written in the CRC expected value information register 129.”) (¶ [0064]: “The display control apparatus 1 shown in FIG. 6 substantially differs from that shown in FIG. 2 in that the cyclic redundancy check can be performed over a plurality of regions simultaneously because a plurality of comparison control units denoted by reference numerals 106a to 106n is provided,” ¶ [0065]: “Because the comparison control units 106a to 106n are provided in this example, the comparison control unit 106a may perform CRC error detection for the plane-1, the comparison control unit 106b may perform CRC error detection for the plane-2, the comparison control unit 106c may perform CRC error detection for the plane 3, and the comparison control unit 106n may perform CRC error detection for the plane-n. Therefore, the cyclic redundancy check can be performed simultaneously over a plurality of regions.”).
Regarding claim 8 (depends on claim 1), MORINO further teaches, and/or renders obvious:
an expected-value calculation circuit (e.g., ¶ [0062]: “a CRC expected value generation circuit”; ¶ [0062]: “CPU 10.”) that calculates the first expected value and the second expected value based on the first input image data and the second input image data (¶ [0062]: “Although it is assumed in the above example that the expected value (CRC expected value) of the arithmetic processing by the CRC arithmetic processing unit 122 has been preliminarily calculated and stored in the ROM 17, there may be provided a CRC expected value generation circuit and calculation of the CRC expected value by the CRC expected value generation circuit can be added as a process at step S101 in FIG. 5. The CRC expected value may be calculated by the CPU 10.” ¶ [0062]: “Although it is assumed in the above example that the expected value (CRC expected value) of the arithmetic processing by the CRC arithmetic processing unit 122 has been preliminarily calculated and stored in the ROM 17, there may be provided a CRC expected value generation circuit and calculation of the CRC expected value by the CRC expected value generation circuit can be added as a process at step S101 in FIG. 5. The CRC expected value may be calculated by the CPU 10.” NOTE: For the hypothetical 1st and 2nd input image data overlaid to create the output image data shown the drawing provided herein-above in the rejection of claim 1, a first expected value would be calculated from the 1st input image data in 1st area in the output image data. Likewise, a second expected value would be calculated from the 2nd input image data in the 2nd area of the overlaid output image data.).
Regarding claim 9 (depends on claim 8), MORINO further teaches, and/or renders obvious:
wherein the expected-value calculation circuit includes
a first-expected-value calculation circuit (e.g., ¶ [0062]: “a CRC expected value generation circuit”; ¶ [0062]: “CPU 10.”) that calculates the first expected value from the first input image data (¶ [0062]: “Although it is assumed in the above example that the expected value (CRC expected value) of the arithmetic processing by the CRC arithmetic processing unit 122 has been preliminarily calculated and stored in the ROM 17, there may be provided a CRC expected value generation circuit and calculation of the CRC expected value by the CRC expected value generation circuit can be added as a process at step S101 in FIG. 5. The CRC expected value may be calculated by the CPU 10.” NOTE: For the hypothetical 1st and 2nd input image data overlaid to create the output image data shown the drawing provided herein-above in the rejection of claim 1, the first expected value would be calculated from the 1st input image data.),
an expected-value-calculation-area determination circuit (¶ [0054]: “CRC expected values for images corresponding to the comparison region are preliminarily calculated and stored in the ROM 17 as a table or the like in association with the image to be compared” ¶ [0061]: “the setting information of the comparison region which is the target of the CRC arithmetic processing, and the CRC expected value information corresponding to the comparison region are preliminarily stored in the ROM 13” [sic, ROM 17].) that determines whether each pixel of the second input image data belongs to the second area (¶ [0035]: “According to the above configuration, arithmetic processing for cyclic redundancy check is performed over the selected region by selecting a region of the image data based on the comparison region information for specifying an arbitrary region of the image displayed on the display unit as a target region of the cyclic redundancy check. Error detection by the cyclic redundancy check is performed only on the target region of the cyclic redundancy check, and thus it suffices to prepare as many expected values of the arithmetic processing result for the cyclic redundancy check as the number of states of the cyclic redundancy check target region (comparison region).” ¶ [0039]: “an expected value information register (129) which holds an expected value of the results of the arithmetic processing by the arithmetic processing unit, and an expected value update information register (139) which holds update information of the expected value in the expected value information register can be provided. The information held in the selection information register is updated by the information held in the selection update information register in synchronization with a vertical synchronizing signal of the display unit, and the information held in the comparison region information registers is updated by the information held in the comparison region update information register in synchronization with a vertical synchronizing signal of the display unit. The information held in the expected value information register is updated by the information held in the expected value update information register in synchronization with a vertical synchronizing signal of the display unit.” ¶ [0054]: “Images in the comparison region differ according to the combination of planes. Therefore, CRC expected values for images corresponding to the comparison region are preliminarily calculated and stored in the ROM 17 as a table or the like in association with the image to be compared. An image to be displayed on the display unit 30 is recognized by the CPU 10. When the image data to be displayed is read from the ROM 17 and transmitted to the image output control unit 100, the CRC expected value for the image corresponding to the comparison region is read from the table in the ROM 17 and written in the CRC expected value information register 129.” ¶ [0057]: “Furthermore, the CPU 10 performs setting of the comparison control unit 106 according to setting information in the ROM 17 (S106). For example, comparison region information is set in the comparison region information register 128, and a CRC expected value corresponding to the comparison region is obtained by referring to the table in the ROM 17, which is set in the CRC expected value information register 129.” ¶ [0061]: “As thus described in this example, the setting information of the comparison region which is the target of the CRC arithmetic processing, and the CRC expected value information corresponding to the comparison region are preliminarily stored in the ROM 13. According to the comparison region information in the ROM 13, the CRC arithmetic processing is performed over the comparison region set in the comparison region information register 128 and, because the computation result is compared with the CRC expected values, it suffices to prepare as large a data capacity for the CRC expected values in the ROM 13 as the number of states of the comparison region which is the target of the CRC computation.” ¶ [0062]: “Although it is assumed in the above example that the expected value (CRC expected value) of the arithmetic processing by the CRC arithmetic processing unit 122 has been preliminarily calculated and stored in the ROM 17, there may be provided a CRC expected value generation circuit and calculation of the CRC expected value by the CRC expected value generation circuit can be added as a process at step S101 in FIG. 5. The CRC expected value may be calculated by the CPU 10.”), and
a second-expected-value calculation circuit (e.g., ¶ [0062]: “a CRC expected value generation circuit”; ¶ [0062]: “CPU 10.”) that calculates the second expected value for the pixel of the second input image data determined to belong to the second area (¶ [0064]: “The display control apparatus 1 shown in FIG. 6 substantially differs from that shown in FIG. 2 in that the cyclic redundancy check can be performed over a plurality of regions simultaneously because a plurality of comparison control units denoted by reference numerals 106a to 106n is provided” NOTE: Thus, as shown in FIG. 6, in the same way a first arbitrary target region can be set and tested, a second arbitrary target region can likewise be set and tested simultaneously using a second comparison control unit.. For instance, the 1st area and the 2nd area in the overlaid output image data shown in the hypothetical scenario in the drawing provided herein-above can simultaneously be error checked in the same way using two of the parallel comparison control units 106a-106n.).
Regarding claim 13 (depends on claim 1), MORINO discloses a display system (FIG. 6) comprising:
the circuit device according to claim 1 (FIG. 6: “DISPLAY OUTPUT CONTROL UNIT” 100. See the rejection of claim 1 herein-above.); and a display device on which the output image data is displayed (FIG. 6: “DISPLAY UNIT” 30.).
Regarding claim 14 (depends on claim 13), MORINO discloses:
wherein the display device is a head-up display (¶ [0048]: “The display unit 30 is a liquid crystal display installed on the dashboard, although not particularly limited thereto.” ¶ [0064]: “the display unit 30”), a meter panel (¶ [0006]: “An instrument panel is installed on the dashboard of an automobile. The term instrument panel refers to a gauge panel having a speedometer” ¶ [0008]: “a graphic display instrument panel” ¶ [0048]: “an instrument panel on a dashboard of an automobile,” ¶ [0048]: “The display unit 30 is a liquid crystal display installed on the dashboard, although not particularly limited thereto.” ¶ [0064]: “the display unit 30”), a center information display (¶ [0011]: “a display unit,” ¶ [0048]: “an instrument panel on a dashboard of an automobile,” ¶ [0048]: “The display unit 30 is a liquid crystal display installed on the dashboard, although not particularly limited thereto.” ¶ [0064]: “the display unit 30”), or an electronic mirror (¶ [0011]: “a display unit,” ¶ [0048]: “The display unit 30 is a liquid crystal display installed on the dashboard, although not particularly limited thereto.” ¶ [0064]: “the display unit 30”).
Allowable Subject Matter
Claims 2 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
At present, it is not apparent to the examiner which part of the application could serve as a basis for new and allowable claims. However, should the applicant nevertheless regard some particular matter as patentable, the examiner encourages applicant to appropriately amend the claims to include such matter and to indicate in the REMARKS the difference(s) between the prior art and the claimed invention as well as the significance thereof.
Furthermore, should applicant decide to amend the claims, examiner respectfully requests that the applicant please indicate in the REMARKS from which page(s), line(s) or claim(s) of the originally filed application that any amendments are derived. See MPEP § 2163(II)(A) (There is a strong presumption that an adequate written description of the claimed invention is present in the specification as filed, Wertheim, 541 F.2d at 262, 191 USPQ at 96; however, with respect to newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims.).
A shortened statutory period for reply to this action is set to expire THREE MONTHS from the mailing date of this action. Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 USC § 133).
Relevant Prior Art
The following prior art, although not relied upon, is made of record since it is considered pertinent to applicant's disclosure:
Gyllensward (US 20150277838 A1) discloses a display controlled by a display drive signal (S2) generated based on an input signal (S1) encoding a safety-critical quantity. A checksum is computed based on the display drive signal and is used to verify the rendering process by which the display drive signal has been produced. In order for the checksum to depend on the safety-critical quantity only, the checksum is computed based on a filtered display drive signal in which pixels with a certain value have been excluded. In embodiments of the invention, safety-noncritical quantities are represented using colors that are due to be excluded. Similarly, a checksum for verifying a given quantity can be made independent of other quantities represented in adjacent screen areas by representing the latter using excluded colors. In other embodiments, pixel values corresponding to particular pixel positions may be excluded from contributing.
HARA (US 20180240397 A1) discloses a display driver including: an interface unit that receives image data; an error detection unit that performs error detection on the received image data; and a drive circuit that drives an electro-optical panel based on the image data. The driver outputs a result of the error detection to an external device.
KIKUTA et al. (US 20190013826 A1) discloses a circuit device including: an interface unit that receives image data; and an error detection unit that performs error detection. The interface unit receives the image data including display image data and error detection data that includes at least position information regarding an error detection region, and the error detection unit performs the error detection on the display image data based on the display image data of the error detection region that is specified by the position information.
WANG (US 20190286115 A1) discloses an object-based integrity verification method for detecting hazardously misleading information contained in an output image of a graphics processing unit comprises steps of: identifying a plurality of safety-critical graphic objects in the output image; assigning each safety-critical graphic object an object ID code; creating an object verification database; rendering a monochrome reference ID code image using object ID code as its color component; verifying the location, shape and color information for each safety-critical graphic object, and tracking the visibility and overlaying property between safety-critical graphic objects using the monochrome reference ID code image; detecting and evaluating failure condition; and annunciating the failure condition with proper warning level and appropriate corrective action.
WIERCIENSKI et al. (US 20220020340 A1) discloses apparatus for data processing, e.g., a display processing unit (DPU), which may receive data including a plurality of data bits, the data being associated with at least one data source. The apparatus may also determine whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI). The apparatus may also detect an adjustment amount of the received data when at least a portion of the data corresponds to priority data, the data being displayed or stored based on the detected adjustment amount.
LERZER et al. (US 20220144298 A1) discloses a device for providing image data of an image to be output on a display apparatus in a motor vehicle, the device including an integrated circuit, which includes a computing unit as a component in a first circuit section and a superimposition unit as a component in a second circuit section. The computing unit determines first partial image data relating exclusively to a portion of the image that is safety-relevant. The superimposition unit superimposes second partial image data that are not safety-relevant onto the first partial image data in such a way that the image data in the entire portion of the image, or in regions of the portion for which the first partial image data are not transparent, are predefined by the first partial image data.
OBARA et al. (US 20220319464 A1) discloses a video processing device including a receiver that successively receives input images, each having a prescribed overlapping image superimposed in one or more areas thereof, a compositing image generation unit that successively generates compositing images based on the external information, a video compositing unit that successively generates composite images, a compositing abnormality detection unit that determines whether one or more areas of the composite image have abnormality or not, a comparison unit that compares the one or more areas of the input image with those of the composite image to determine whether or not the respective areas match, if it is determined that the composite image have no abnormalities, and an output control unit that outputs the input image if it is determined that the respective areas match, and outputs the composite image when it is determined that the respective areas do not match.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT PEREN who can be reached by telephone at (571) 270-7781, or via email at vincent.peren@uspto.gov. The examiner can normally be reached on Monday-Friday from 10:00 A.M. to 6:00 P.M.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KING POON, can be reached at telephone number (571)272-7440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VINCENT PEREN/
Examiner, Art Unit 2617
/KING Y POON/Supervisory Patent Examiner, Art Unit 2617
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