Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Interpretation
Independent claims 1 and 12 introduce inverters labeled, zeroth, first, second, and third, and then skip to sixth and seventh without introducing fourth and fifth inverters until dependent claims 2 and 13 respectively.
The Examiner notes that the introduction of a sixth and seventh inverter in the independent claim inherently incorporates a fourth and fifth inverter into the claim despite them not being explicitly claimed. If this interpretation is not desired, the claims should be amended to label the sixth and seventh inverters as “fourth” and “fifth”, and a corresponding amendment to the fourth and fifth inverters being introduced as the “sixth” and “seventh”, as well as any other corresponding amendments to maintain consistency throughout the claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Per Claims 11 and 19, it is unclear how the zeroth and first inverters, each comprise two inverter units connected in parallel. Similarly, it is unclear how the second and third inverters each comprise four respective inverter units connected in parallel.
The Specification and Drawings do not appear to support the “inverter units” as being anything different than the “inverters”.
- For examination purposes, the “inverter units” will be interpreted as the “inverters” themselves.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8-12, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Le et al. U.S. PGPUB No. 2010/0271099 (cited in IDS dated 2/28/2025).
Per Claim 1, Le discloses:
a dual-rail buffer circuit (Paragraph 40, Fig. 5 (reproduced below); rails 504 and 508), comprising:
a first input port configured to receive a first input signal (Paragraph 41; initial input 516);
a second input port configured to receive a second input signal (Paragraph 41; initial input 520);
a first output port coupled via a first channel to the first input and configured to output a first output signal (Paragraphs 37, 38, and 47, Figure 5; N2 represents an output port outputting a signal on a channel corresponding to rail/channel 504.);
a second output port coupled via a second channel to the second input and configured to output a second output signal (Paragraphs 37, 38, and 47, Figure 5; N2_BAR represents an output port outputting a signal on a channel corresponding to rail/channel 508.);
a zeroth inverter and a second inverter comprised within the first channel between the first input and the first output (Fig. 5; The inverters on rail/channel 504 located at stages 502a and 502b.);
a first inverter and a third inverter comprised within the second channel between the second input and the second output (Fig. 5; The inverters on rail/channel 508 located at stages 510a and 510b);
a sixth inverter, wherein the sixth inverter is connected to the first channel after the zeroth and second inverters, and wherein the sixth inverter is connected to the second channel before the first and third inverters (Fig. 5; inverter 518);
and a seventh inverter, wherein the seventh inverter is connected to the first channel before the zeroth and second inverters, and wherein the seventh inverter is connected to the second channel after the first and third inverters (Fig. 5, inverter 514).
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Per Claim 8, Le discloses the dual-rail buffer circuit of claim 1, wherein the dual-rail buffer circuit is configured within a global clock distribution network (Paragraph 73, Figure 10; “This interpretation of the delay chain 500 is reflected in the inputs to the flip-flops 1008 associated with the precision sampler 1004. The odd numbered flip-flops 1008, those associated with stages N1, N3, N5 etc. may be "cross-wired." Specifically, the data delay rail 504 is connected to the data complement 1118b input of the corresponding flip-flop 1008. Similarly, the data complement rail 508 is connected to the data input 1118a of the corresponding flip-flop 1008. In contrast, the even numbered stages, those associated with stages N2, N4, N6 etc., are not "cross-wired." Specifically, the data delay rail 504 is connected to the data input 1116 and the data complement rail 508 is connected to the data complement 1118b input at the corresponding flip-flop 1008. In this way, the precision sampler 1004 will interpret the delay chain 500 in a consistent manner.” – A “global clock distribution network” is a broad term and Le’s delay chain 500 providing clock inputs from the various stages of the chain to various components of the integrated circuit reads on this limitation.).
Per Claim 9, Le teaches the dual rail buffer circuit of claim 1, wherein the dual-rail buffer circuit is configured within the global clock distribution network as a modular unit (Figures 5 and 10; Delay chain 500 implemented within integrated circuit of Fig. 10.) comprising the dual-rail buffer circuit (Figures 5 and 10; Delay chain 500 comprises buffer circuits/inverters therewithin.) and a transmission line (Rails 504 and 508).
Per Claim 10, Le discloses the dual-rail buffer circuit of claim 1, wherein the sixth and seventh inverters provide fractional nonlinear feed-forward equalization to the first and second outputs (Paragraph 41).
Per Claim 11, Le discloses the dual-rail buffer circuit of claim 1, wherein the zeroth and first inverters each comprise two respective inverter units connected in parallel, and wherein the second and third inverters each comprise four respective inverter units connected in parallel, wherein each inverter unit has a same strength as the sixth and seventh inverters (Figure 5, Paragraphs 42 and 43 disclose the inverter drive strength).
Per Claim 12, Le discloses:
a global clock distribution network (Paragraph 73, Figure 10; See citation from claim 8 above. A “global clock distribution network” is a broad term and Le’s delay chain 500 providing clock inputs from the various stages of the chain various components of the integrated circuit reads on this limitation.), comprising:
a plurality of standardized units, wherein each standardized unit comprises a dual-rail buffer circuit coupled to a transmission line (Paragraph 40, Fig. 5 (reproduced below); rails 504 and 508 represent a transmission line), wherein the dual-rail buffer circuit comprises:
a first input port configured to receive a first input signal (Paragraph 41; initial input 516);
a second input port configured to receive a second input signal (Paragraph 41; initial input 520);
a first output port coupled via a first channel to the first input and configured to output a first output signal (Paragraphs 37, 38, and 47, Figure 5; N2 represents an output port outputting a signal on a channel corresponding to rail/channel 504.);
a second output port coupled via a second channel to the second input and configured to output a second output signal (Paragraphs 37, 38, and 47, Figure 5; N2_BAR represents an output port outputting a signal on a channel corresponding to rail/channel 508.);
a zeroth inverter and a second inverter comprised within the first channel between the first input and the first output (Fig. 5; The inverters on rail/channel 504 located at stages 502a and 502b.);
a first inverter and a third inverter comprised within the second channel between the second input and the second output (Fig. 5; The inverters on rail/channel 508 located at stages 510a and 510b);
a sixth inverter, wherein the sixth inverter is connected to the first channel after the zeroth and second inverters, and wherein the sixth inverter is connected to the second channel before the first and third inverters (Fig. 5; inverter 518);
and a seventh inverter, wherein the seventh inverter is connected to the first channel before the zeroth and second inverters, and wherein the seventh inverter is connected to the second channel after the first and third inverters (Fig. 5, inverter 514).
Per Claims 18 and 19, please refer to the above rejection of claims 10 and 11, respectively, as the limitations are substantially similar and the mapping of the limitations is equally applicable.
Per Claim 20, Le discloses the global clock distribution network of claim 12, further comprising: a plurality of T connections (See Fig. 5 below; T connections are broadly interpreted as a communication line connected to three different inverters.), wherein the plurality of standardized units and the plurality of T connections are configured in a tree structure comprising a plurality of stages (Paragraph 41, Fig. 5; stages 502a-n), wherein the modular global clock distribution network is configured to provide synchronized timing information to each of a plurality of circuit modules (Paragraph 73, Figure 10; A “global clock distribution network” is a broad term and Le’s delay chain 500 providing clock inputs from the various stages of the chain to various components of the integrated circuit reads on this limitation. The flip-flops 1008 read on “a plurality of circuit modules”), and wherein a length of the standardized units is determined based at least in part on a pitch length of the circuit modules (Figures 3, 5, and 10, The number of stages 308/502 read on the claimed “length of the standardized units” as they would be equivalent to the “repetition distance” as described in paragraph 120 of the disclosed Specification: “the pitch length of the circuit modules is a repetition distance of the circuit modules in the multiprocessor array”).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 3, 6, 7, 13, 14, 16, and 17, are rejected under 35 U.S.C. 103 as being unpatentable over Le et al. U.S. PGPUB No. 2010/0271099 in view of Jones et al. U.S. PGPUB No. 2013/0135017.
Per Claim 2, Le discloses the dual-rail buffer circuit of claim 1, further comprising: a fourth inverter (Fig. 9, inverter 920) and a fifth inverter (Fig. 9, inverter 924) coupled to the first channel and the second channel (Fig. 9; rails/channels 904 and 908), and wherein the fourth and fifth inverters are coupled to the first and second channels with opposite polarity (Fig. 9 shows opposite polarity for each of inverters 920 and 924).
Le does not specifically disclose wherein the fourth and fifth inverters are coupled to the first channel in between the zeroth and second inverters, wherein the fourth and fifth inverters are coupled to the second channel in between the first and third inverters.
However, Jones teaches a cross-coupled inverter pair connected between inverters in a similar setup as claimed (Fig. 3 (reproduced below), Paragraphs 61-64)
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- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the cross-coupled inverter pair of Jones in the delay chain of Le because the inventions are of a common field of endeavor, have a common assignee (Oracle/Sun Microsystems), and Jones teaches that the cross-coupled inverter pair (a jamb-latch circuit) offers better metastability resolution performance across the dual rail configuration (Jones, Paragraph 62).
Per Claim 3, Le discloses the dual-rail buffer circuit of claim 2, wherein the fourth and fifth inverters have a first strength that is less than respective strengths of the zeroth, first, second, third, sixth and seventh inverters (Paragraph 42, “drive strength”. Fig. 9 shows the cross-coupled inverters having a drive strength of 1x, whereas the inverters of the dual-rail channels having a driver strength of 4x.).
Per Claims 6 and 7, Le teaches that various inverter strengths can be used (Paragraph 43), but does not specifically teach the strengths of “half as large” or “twice as large”, as required by the claim.
However, Jones teaches inverters of various strengths, including 4x, 8x, 16x, and 24x (Paragraph 70, Figure 4A), which encompass both the half and twice as large limitations.
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the Jones’ specific inverter strength values within the inverter system of Le because Jones teaches that different transistor/inverter strengths can be implemented depending on the use of the synchronizer circuit (Jones, Paragraph 52)
Per Claims 13, 14, 16, and 17, please refer to the above rejection of claims 2, 3, 6, and 7, respectively, as the limitations are substantially similar and the mapping of the limitations is equally applicable.
Allowable Subject Matter
Claims 4 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Per Claims 4 and 15, no combination of Le and the prior art specifically teaches the previously claimed fourth through seventh inverters as being tri-state-inverters in combination with their connection with an “enable input signal” that is controllable to enable and disable the fourth through seventh inverters, when considered in combination with the limitations of independent claims 1 and 12.
Claim 5 inherits the allowable subject matter of Claim 4.
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175