DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application claims priority to Japanese Patent Application No. 2023-0169038, filed 09/29/2023. The priority claim is acknowledged by the Examiner.
Electronic receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 on 12/02/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Examiner’s Note
The Examiner cites particular columns, paragraphs, figures, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may also apply. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 4 and 14, the claim recites “the second arithmetic device stores an address selected according to calculated third data in the address register”. Claim 4 depends from claim 1, which recites calculating first data, but does not recite calculating or otherwise obtaining third data. The claim does not identify the source of the third data or how the third data is calculated. Accordingly, a person of ordinary skill in the art would not be able to recognize what constitutes the claimed “calculated third data” or how the claimed “calculated third data” is related to the other data recited in the claim, causing the metes and bounds of the claimed invention to be unclear to a person of ordinary skill in the art. For purposes of examination, the Examiner assumes the third data is calculated from execution of the fifth instruction on the first arithmetic device (1st device executes 1st instruction resulting in 1st data [Wingdings font/0xE0] 2nd device await instruction is 2nd instruction, upon syncing, executes 3rd instruction using 1st data resulting in 2nd data [Wingdings font/0xE0] 1st device await instruction is 4th instruction, upon syncing, executes 5th instruction using 2nd data, which the Examiner assumes results in the claimed 3rd data).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7, 11-12, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20220350774 A1) hereafter Wang in view of Foley (US 20230342152 A1).
Regarding claim 1, Wang teaches:
A processor (Paragraph 170; “The electronic device includes: at least one processor”) comprising:
a first arithmetic device configured to execute a first instruction (Paragraph 33; “The first coprocessor acquires a first relationship instruction, and executes at least one computing instruction acquired before the first relationship instruction based on the first relationship instruction. The first coprocessor sends acknowledgment information based on the first relationship instruction in response to completing executing the at least one computing instruction”, the first coprocessor corresponding to the first arithmetic device that executes at least one computing instruction, corresponding to executing a first instruction.);
and a second arithmetic device configured to execute a second instruction and a third instruction (Paragraph 44; “That is, the second coprocessor is in a blocking state of stopping acquiring and executing the second computing instruction posterior to the second relationship instruction before receiving the acknowledgment information, so that the second coprocessor waits for an acknowledgment signal sent by the first coprocessor before starting a specific computing task.”, the await step corresponding to the second instruction based on the later limitation defining the second instruction being one for waiting for issuance of first synchronization information, and the specific computing task corresponding to the third instruction.), wherein:
the first arithmetic device calculates first data by executing the first instruction (Paragraph 33; “The first coprocessor acquires a first relationship instruction, and executes at least one computing instruction acquired before the first relationship instruction based on the first relationship instruction. The first coprocessor sends acknowledgment information based on the first relationship instruction in response to completing executing the at least one computing instruction”, and Paragraph 52; “In the embodiment of the disclosure, the dependency relationship means that the second coprocessor relies on the execution result of the first coprocessor. Thus, the first coprocessor may send the acknowledgment information to the second coprocessor after executing the corresponding result.”, where reliance on the execution result of the first coprocessor means reliance on the data resulting from execution of the first instruction on the first arithmetic device.);
and the second arithmetic device stops execution of the third instruction based on the second instruction which is an instruction for waiting issuance of first synchronization information, and thereafter executes the third instruction, based on the issuance of the first synchronization information from the first arithmetic device (Paragraph 44; “the second coprocessor is in a blocking state of stopping acquiring and executing the second computing instruction posterior to the second relationship instruction before receiving the acknowledgment information, so that the second coprocessor waits for an acknowledgment signal sent by the first coprocessor before starting a specific computing task.”, the second coprocessor being in a blocked state and awaiting corresponding to the second instruction for waiting issuance of synchronization information. Upon receiving acknowledgement information, corresponding to synchronization information, the second coprocessor begins the specific computing task, corresponding to the third instruction. Paragraph 52 confirms that the execution relies on the result of the first coprocessor, corresponding to using the first data; “In the embodiment of the disclosure, the dependency relationship means that the second coprocessor relies on the execution result of the first coprocessor. Thus, the first coprocessor may send the acknowledgment information to the second coprocessor after executing the corresponding result.”).
While Wang implies that data from the first instruction is utilized in execution for the third instruction, Wang does not explicitly disclose that the third instruction uses the first data.
However, Foley teaches:
the third instruction uses the first data (Paragraph 42; “The operations that are being executed can include data dependent operations. In embodiments, the plurality of control words includes two or more data dependent branch operations. The branch operation can include two or more branches, where a branch is selected based on an operation such as an arithmetic or logical operation.”, where the next operation is dependent on the branch which is based on a previous operation).
Wang and Foley are considered to be analogous to the claimed invention because they are in the same field of instruction execution. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Wang and Foley to have the third instruction use the first data because dependent operations are known in the art to be able to be implemented to have previous instructions produced by earlier operations be used as input to perform subsequent operations, whose implementation would yield the predictable result of allowing the subsequent instruction to operate on the data produced by the previous instruction.
Claim 11 recites similar limitations as those of claim 1. Claim 11 is rejected for similar reasons as those of claim 1.
Regarding claim 2, Wang in view of Foley teach the apparatus of claim 1. Wang teaches:
an instruction supply control circuit (Paragraph 31; “The heterogeneous processor in the related art synchronizes the coprocessors by a control unit”, and Paragraph 178; “Various implementation modes of systems and technologies described herein may be implemented in a digital electronic circuit system, an integrated circuit system, a field programmable gate array (FPGA), a dedicated application specific integrated circuit (ASIC)”).
Wang teaches the forward direction: a first arithmetic device that calculates first data by executing a first instruction and stopping supply of instructions based on an instruction for waiting issuance of synchronization information, and supplying the instruction that uses the first data to the second arithmetic device based on the issuance of synchronization information (see Claim 1).
Wang does not expressly disclose performing the operations in the claimed reverse order, wherein the second device calculates second data by executing the third instruction, the instruction supply control circuit stops supply of a fifth instruction to the first arithmetic device based on a fourth instruction for waiting issuance of second synchronization information, and thereafter supplying the fifth instruction that utilizes the second data to the first arithmetic device based on the issuance of the second synchronization information.
However, Foley teaches:
operations between the devices may be dependent on each other (Paragraph 81; “In embodiments, the first control unit and the second control unit can operate in lockstep on a cycle-by-cycle basis. The lockstep basis can enable sharing of input data, exchange of control signals, and so on. The tasks and subtasks that are executed can be dependent on one another.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have performed a second execution of the disclosed process of claim 1 such that the second device executes the third instruction, and upon completion of the third instruction, to which a fourth instruction waits for issuance of second synchronization information, supplies the fifth instruction that uses the second data to the first arithmetic device. Given Foley teaches that the systems may operate in lockstep and have tasks that are dependent upon one another, a person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the inter-device process could be executed again with the roles of the units reversed such that the operation performed by the second device provides the dependency for a subsequent operation performed by the first device, representing a known process. Performing the known process a second time in the opposite direction would have yielded the predictable result of providing the first device with the result of the second device’s operation for execution of the subsequent fifth instruction on the first device.
Claim 12 recites similar limitations as those of claim 2. Claim 12 is rejected for similar reasons as those of claim 2.
Regarding claim 7, Wang in view of Foley teach the apparatus of claim 1. Wang teaches:
wherein the second instruction is a wait instruction or a polling instruction (Paragraph 44; “the second coprocessor is in a blocking state of stopping acquiring and executing the second computing instruction posterior to the second relationship instruction before receiving the acknowledgment information, so that the second coprocessor waits for an acknowledgment signal sent by the first coprocessor before starting a specific computing task.”, the waiting for the acknowledgement signal corresponding to the second instruction to wait before further execution).
Claim 17 recites similar limitations as those of claim 7. Claim 17 is rejected for similar reasons as those of claim 7.
Claims 3-6, 8, 13-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Foley, further in view of Burger et al. (US 20170083331 A1) hereafter Burger.
Regarding claim 3, Wang in view of Foley teach the apparatus of claim 1. Wang teaches:
an instruction supply control circuit (Paragraph 31; “The heterogeneous processor in the related art synchronizes the coprocessors by a control unit”, and Paragraph 178; “Various implementation modes of systems and technologies described herein may be implemented in a digital electronic circuit system, an integrated circuit system, a field programmable gate array (FPGA), a dedicated application specific integrated circuit (ASIC)”);
the first arithmetic device (Paragraph 33; first coprocessor);
the second arithmetic device (Paragraph 44; second coprocessor);
performing actions based on the issuance of the first synchronization information (Paragraph 44; “the second coprocessor is in a blocking state of stopping acquiring and executing the second computing instruction posterior to the second relationship instruction before receiving the acknowledgment information, so that the second coprocessor waits for an acknowledgment signal sent by the first coprocessor before starting a specific computing task.”, the second coprocessor being in a blocked state and awaiting corresponding to the second instruction for waiting issuance of synchronization information. Upon receiving acknowledgement information, corresponding to synchronization information, the second coprocessor begins the specific computing task).
Wang in view of Foley does not teach the second arithmetic device includes an address register configured to hold a read address of an instruction from a storage device; the second arithmetic device stores an address selected according to the first data in the address register, based on the issuance of the first synchronization information; the instruction supply control circuit reads a fourth instruction from a storage area of the storage device indicated by the address stored in the address register; the instruction supply control circuit supplies the fourth instruction read from the storage area to the first arithmetic device.
However, Burger teaches:
an address register configured to hold a read address of an instruction from a storage device (Paragraph 103; “method includes executing a load linked instruction that causes a processor to read a data value from an address location in a memory unit, store the address location in a load linked address register,”, and Paragraph 124 confirms this may come from a storage device, “In a distributed computing environment, program modules (including executable instructions for block-based instruction blocks) may be located in both local and remote memory storage devices.”);
stores an address selected according to the first data in the address register (Paragraph 103; “method includes executing a load linked instruction that causes a processor to read a data value from an address location in a memory unit, store the address location in a load linked address register,”, explicitly disclosing storage of an address for an instruction in a linked address register, thereby being selected according to the specific memory address of the first data.);
reads a fourth instruction from a storage area of the storage device indicated by the address stored in the address register (Paragraph 99; “data stored at the memory address specified by the right operand 820 is read (MEM[ROP] 830)”, the memory corresponding to the storage device);
supplies the fourth instruction read from the storage area (Paragraph 99; “data stored at the memory address specified by the right operand 820 is read (MEM[ROP] 830) and then sent by the load link instruction to a target instruction (T0).”).
Wang, Foley, and Burger are considered to be analogous to the claimed invention because they are in the same field of instruction execution. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Wang, Foley, and Burger to have an address register configured to hold a read address of an instruction, store an address selected according to the first data, read an instruction from a storage area of the storage device indicated by the address stored in the address register, and supply the instruction read from the storage area. A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that using an address register to store addresses selected according to data and retrieving an instruction from a storage area indicated by the stored address is a known method in the art because storing the selected address provides a location from which the corresponding instruction may be retrieved, whose implementation would yield the predictable result of retrieving and supplying the instruction associated with the selected address.
Claim 13 recites similar limitations as those of claim 3. Claim 13 is rejected for similar reasons as those of claim 3.
Claim 4 recites similar limitations as those of claim 3, the address being selected according to the third data instead of the first, and not being based on the issuance of the first synchronization information.
Foley teaches:
operations between the devices may be dependent on each other (Paragraph 81; “In embodiments, the first control unit and the second control unit can operate in lockstep on a cycle-by-cycle basis. The lockstep basis can enable sharing of input data, exchange of control signals, and so on. The tasks and subtasks that are executed can be dependent on one another.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have performed a second execution of the disclosed process of claim 3 such that the second device executes the third instruction, and upon completion of the third instruction, to which a fourth instruction waits for issuance of second synchronization information, supplies the fifth instruction that uses the second data to the first arithmetic device, resulting in the 3rd data from which the address is selected. Given Foley teaches that the systems may operate in lockstep and have tasks that are dependent upon one another, a person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the inter-device process could be executed again with the roles of the units reversed such that the operation performed by the second device provides the dependency for a subsequent operation performed by the first device, representing a known process. Performing the known process a second time in the opposite direction would have yielded the predictable result of providing the first device with the result of the second device’s operation for execution of the subsequent fifth instruction on the first device using the calculated third data from which the address may be selected.
Claim 14 recites similar limitations as those of claim 4. Claim 14 is rejected for similar reasons as those of claim 4.
Regarding claim 5, Wang in view of Foley, further in view of Burger teach the apparatus of claim 3. Wang teaches:
the instruction supply control circuit (Paragraph 31; “The heterogeneous processor in the related art synchronizes the coprocessors by a control unit”, and Paragraph 178; “Various implementation modes of systems and technologies described herein may be implemented in a digital electronic circuit system, an integrated circuit system, a field programmable gate array (FPGA), a dedicated application specific integrated circuit (ASIC)”).
Foley teaches:
an instruction buffer (Paragraph 59; “The system block diagram 400 can include lower load buffers 422 and upper load buffers 442. The load buffers can provide temporary storage for memory load data so that it is ready for low latency access by the compute element array 410.”, in which Paragraph 81 confirms that these may be instructions, “The executing component 760 can include control and functions for executing instructions within the array of compute elements”).
Burger teaches:
a FIFO configured to hold the instruction read from the storage device (Paragraph 58; “a reference to a respective instruction can be pushed onto a ready queue when the dependencies have been met for the respective instruction, and ready instructions can be scheduled in a first-in first-out (FIFO) order from the ready queue”. Paragraph 124 confirms this may come from a storage device, “In a distributed computing environment, program modules (including executable instructions for block-based instruction blocks) may be located in both local and remote memory storage devices.”).
Claim 15 recites similar limitations as those of claim 5. Claim 15 is rejected for similar reasons as those of claim 5.
Regarding claim 6, Wang in view of Foley, further in view of Burger teach the apparatus of claim 3. Wang teaches:
the instruction supply control circuit (Paragraph 31; “The heterogeneous processor in the related art synchronizes the coprocessors by a control unit”, and Paragraph 178; “Various implementation modes of systems and technologies described herein may be implemented in a digital electronic circuit system, an integrated circuit system, a field programmable gate array (FPGA), a dedicated application specific integrated circuit (ASIC)”).
Foley teaches:
an instruction buffer (Paragraph 59; “The system block diagram 400 can include lower load buffers 422 and upper load buffers 442. The load buffers can provide temporary storage for memory load data so that it is ready for low latency access by the compute element array 410.”, in which Paragraph 81 confirms that these may be instructions, “The executing component 760 can include control and functions for executing instructions within the array of compute elements”);
a plurality of FIFOs configured to hold instructions read from the memory device (Paragraph 64; “The compute elements can be coupled to load queues such as load buffers 516 and load buffers 518. The load buffers, or load queues, can be coupled to the L1 data caches as discussed previously.”, where a person of ordinary skill in the art would recognize the implementation of generic queues to have FIFO functionality. Paragraph 81 confirms that these may be instructions, “The executing component 760 can include control and functions for executing instructions within the array of compute elements”).
Burger teaches:
a selection control circuit configured to select a location to which an instruction is input and from which an instruction is output (Paragraph 67; “For example, each cycle, the decoder(s) write instructions' decoded ready state and decoded instructions into one or more instruction windows, selects the next instruction to issue”, in which the decoder performs the instruction selection and may be implemented as a circuit as evidenced by Paragraph 3; “described techniques and tools can be implemented in a digital signal processor, microprocessor, application-specific integrated circuit (ASIC), a soft processor (e.g., a microprocessor core implemented in a field programmable gate array (FPGA) using reconfigurable logic), programmable logic, or other suitable logic circuitry”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Wang, Foley, and Burger, to have implemented the selection control of Burger on the plurality of FIFOs of Foley. A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that because multiple FIFOs exist in which instructions may exist, a selection control would be a known method to ensure that no one FIFO is selected more often than the others, yielding the predictable result of avoiding overloading any single FIFO with requests, and improving system reliability.
Claim 16 recites similar limitations as those of claim 6. Claim 16 is rejected for similar reasons as those of claim 6.
Claim 8 recites similar limitations as those of claim 3, additionally reciting an instruction memory, supplying the first instruction to the first arithmetic device instead of the second, supplying the first instruction to the first instruction device instead of the fourth, and based on storage of the address in the address register. Foley teaches:
operations between the devices may be dependent on each other (Paragraph 81; “In embodiments, the first control unit and the second control unit can operate in lockstep on a cycle-by-cycle basis. The lockstep basis can enable sharing of input data, exchange of control signals, and so on. The tasks and subtasks that are executed can be dependent on one another.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have performed another execution of the disclosed process of claim 3 such that the first instruction is provided instead of the fourth instruction. Given Foley teaches that the systems may operate in lockstep and have tasks that are dependent upon one another, a person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the inter-device process could be executed again with the roles of the units reversed such that the operation performed by the second device provides the dependency for a subsequent operation performed by the first device, representing a known process. Performing the known process a second time in the opposite direction would have yielded the predictable result of providing the first device with the first instruction for execution to yield the setting in which the fourth instruction may be executed.
Burger teaches:
an instruction memory (Paragraph 91; “When the instruction block is in the fetch state 620 (e.g., instruction fetch), the mapped processor core fetches computer-readable block instructions from the block-based processors' memory system”);
performing actions based on storage of the address in the address register (Paragraph 100; “When executed, the store conditional instruction will compare the right operand ROP to the address stored in the load linked address register 730 using comparison logic 920. When executed, the store conditional instruction will also check the value of the load linked bit from the load linked bit register 735 using the comparison logic 920. If the address stored in the load linked address register 730 is equal to the ROP value and the load linked bit is set to one (1), then a memory control signal 925 is sent to the memory 750 and result data 930 from the instructions left operand LOP slot is written to the memory 750”, where actions are performed based on the address in the address register comparison returning a match.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Wang, Foley, and Burger, to have supplied the first instruction to the first arithmetic device if the address indicated by the instruction matches that of the stored address in the address register. A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that execution of instructions only if addresses match is a known method in the art for preventing execution of instructions with mismatching addresses, whose implementation would yield the predictable result of ensuring only instructions intended to be executed are properly executed.
Claim 18 recites similar limitations as those of claim 8. Claim 18 is rejected for similar reasons as those of claim 8.
Claims 9-10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Foley, further in view of Burger, further in view of Houdek et al. (US 4903194 A) hereafter Houdek.
Regarding claim 9, Wang in view of Foley, further in view of Burger teach the apparatus of claim 8. Wang teaches:
the instruction supply control circuit (Paragraph 31; “The heterogeneous processor in the related art synchronizes the coprocessors by a control unit”, and Paragraph 178; “Various implementation modes of systems and technologies described herein may be implemented in a digital electronic circuit system, an integrated circuit system, a field programmable gate array (FPGA), a dedicated application specific integrated circuit (ASIC)”);
performing actions based on the issuance of synchronization information (Paragraph 44; “the second coprocessor is in a blocking state of stopping acquiring and executing the second computing instruction posterior to the second relationship instruction before receiving the acknowledgment information, so that the second coprocessor waits for an acknowledgment signal sent by the first coprocessor before starting a specific computing task.”, the second coprocessor being in a blocked state and awaiting corresponding to the second instruction for waiting issuance of synchronization information. Upon receiving acknowledgement information, corresponding to synchronization information, the second coprocessor begins the specific computing task).
Burger teaches:
the address register (Paragraph 103; “method includes executing a load linked instruction that causes a processor to read a data value from an address location in a memory unit, store the address location in a load linked address register”);
reading an instruction from a storage area of the storage device indicated by the address stored in the address register (Paragraph 99; “data stored at the memory address specified by the right operand 820 is read (MEM[ROP] 830)”, the memory corresponding to the storage device);
supplies the instruction read from the storage area (Paragraph 99; “data stored at the memory address specified by the right operand 820 is read (MEM[ROP] 830) and then sent by the load link instruction to a target instruction (T0).”);
performing actions based on storage of the address in the address register (Paragraph 100; “When executed, the store conditional instruction will compare the right operand ROP to the address stored in the load linked address register 730 using comparison logic 920. When executed, the store conditional instruction will also check the value of the load linked bit from the load linked bit register 735 using the comparison logic 920. If the address stored in the load linked address register 730 is equal to the ROP value and the load linked bit is set to one (1), then a memory control signal 925 is sent to the memory 750 and result data 930 from the instructions left operand LOP slot is written to the memory 750”, where actions are performed based on the address in the address register comparison returning a match.).
Wang in view of Foley, further in view of Burger does not teach an area for holding synchronization information.
However, Houdek teaches:
an area for holding synchronization information (Col. 6, lines 1-10; “The I/O hash bits from the I/O generate logic 26 are compared with the high order hash bits in the address register 20 by compare logic 27 which for example can be logical and circuits. If the generated hash bits do not compare with the hash bits from the address register 20, an error condition exists and a signal noting that condition is sent to the I/O unit over line 28. This indicates to the IOP that the address sent for the data transfer was invalid.”, where the hash bits in the address register are utilized for confirming logical information, corresponding to an area for holding synchronization information within the address register where the hash bits are dedicated to indicating the state of the address, thereby providing information used to synchronize the system.).
Wang, Foley, Burger, and Houdek are considered to be analogous to the claimed invention because they are in the same field of instruction execution. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Wang, Foley, Burger, and Houdek to have configured an address register to have an area for holding synchronization information as dedicating register bits to indicator information is a known method in the art that provides a mechanism for storing state information associated with the stored address, whose implementation would yield the predictable result of allowing the indicator information to be maintained in association with the address in the register.
Claim 19 recites similar limitations as those of claim 9. Claim 19 is rejected for similar reasons as those of claim 9.
Regarding claim 10, Wang in view of Foley, further in view of Burger teach the apparatus of claim 8. Foley teaches:
FIFO-based implementation (Paragraph 64; “The compute elements can be coupled to load queues such as load buffers 516 and load buffers 518. The load buffers, or load queues, can be coupled to the L1 data caches as discussed previously.”, where a person of ordinary skill in the art would recognize the implementation of generic queues to have FIFO functionality.).
Burger teaches:
the address register (Paragraph 103; “method includes executing a load linked instruction that causes a processor to read a data value from an address location in a memory unit, store the address location in a load linked address register”).
Wang in view of Foley, further in view of Burger does not teach a plurality of areas for holding addresses and synchronization information.
However, Houdek teaches:
areas for holding an address and synchronization information (Col. 6, lines 1-10; “The I/O hash bits from the I/O generate logic 26 are compared with the high order hash bits in the address register 20 by compare logic 27 which for example can be logical and circuits. If the generated hash bits do not compare with the hash bits from the address register 20, an error condition exists and a signal noting that condition is sent to the I/O unit over line 28. This indicates to the IOP that the address sent for the data transfer was invalid.”, where the hash bits in the address register are utilized for confirming logical information, corresponding to an area for holding synchronization information within the address register where the hash bits are dedicated to indicating the state of the address, thereby providing information used to synchronize the system.).
Wang, Foley, Burger, and Houdek are considered to be analogous to the claimed invention because they are in the same field of instruction execution. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Wang, Foley, Burger, and Houdek to have configured an address register to have an area for holding synchronization information as dedicating register bits to indicator information is a known method in the art that provides a mechanism for storing state information associated with the stored address, whose implementation would yield the predictable result of allowing the indicator information to be maintained in association with the address in the register. Further, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have configured the address register as a FIFO structured queue having a plurality of entries for storing a plurality of addresses and corresponding synchronization information as queues are a known mechanism in the art for storing and processing entries in an ordered sequence, whose implementation would yield the predictable result of allowing the address register to store and maintain a plurality of addresses and corresponding synchronization information in an ordered fashion within the address register.
Claim 20 recites similar limitations as those of claim 10. Claim 20 is rejected for similar reasons as those of claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hoogerbrugge et al. (US 20110093661 A1) discusses acquiring instructions and synchronizing circuits between multiple processor cores, and stalling the second processor core until the first processor core executes the release instruction (Paragraph 45).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH P TRAN whose telephone number is (571)272-6926. The examiner can normally be reached M-TH 4:30 a.m. - 12:30 p.m. PT, F 4:30 a.m. - 8:30 a.m. PT, or at Kenneth.Tran@uspto.gov.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at (571) 270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KENNETH P TRAN/Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
Prosecution Insights