DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Claim Status
Claims 1-20 are currently pending. Claims 1, 5,6, 9, 13, 14, and 17 are amended as per Applicant’s amendment filed on 23 December 2025.
Response to Arguments
Applicant's arguments filed 23 December 2025 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The amended claims are addressed in the rejections below further in view of Peterson (US 20180095680 A1).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6-7 and 14-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Examiner was not able to find support for the limitation “wherein the flash memory portion has remaining blocks mapped to the first indirection unit size” of claims 6 and 14. Examiner found support for multiple IU sizes see instant specification [0279-0280, Fig. 4] but not the limitations as written. Examiner suggests Applicant amend the claims to what is supported by the specification.
Claims 7 and 15 inherit the same issues and are rejected for the same reasoning.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-13, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 20220129189 A1) in view of Peterson (US 20180095680 A1).
Referring to claims 1, 9, and 17, taking claim 1 as exemplary, Zhou teaches
A storage device, comprising: a flash memory portion; ([Zhou abstract, 0057, Fig. 2] data storage method in a flash device and a flash device, where the flash device includes a plurality of flash translation layers (FTLs)) and a storage device controller comprising a flash translation layer (FTL), operatively coupled to the flash memory portion, ([Zhou abstract, 0057, Fig. 2] data storage method in a flash device and a flash device, where the flash device includes a plurality of flash translation layers (FTLs). A flash device 200 includes a receiving module 201, a selection module 202, and a management module 203. The flash device 200 includes a plurality of types of FTLs, each of the plurality of types of FTLs is used to record a mapping from a logical address to a flash physical address, and granularities of logical addresses of the plurality of types of FTLs are different. The receiving module 201 is configured to receive a write operation request. The selection module 202 is configured to select a target FTL from the plurality of types of FTLs based on the received write operation request. The management module 203 is configured to allocate a physical address from the flash device to the received write operation request based on the selected target FTL.) configured to: receive, from a storage system controller, one or more requests to store data in the flash memory portion; ([Zhou abstract, 0057, Fig. 2] The receiving module 201 is configured to receive a write operation request.) determine, from information associated with the one or more requests, an indirection unit size to use in the FTL for mapping the data; ([Zhou abstract, 0057-0059, Fig. 2] The selection module 202 is configured to select a target FTL from the plurality of types of FTLs based on the received write operation request. the selection module 202 is configured to select the target FTL from the plurality of types of FTLs based on at least one of an I/O size of the write operation request, a data type carried in the write operation request, a service type for sending the write operation request, or modification frequency of data in a logical address corresponding to the write operation request. the selection module 202 is configured to separately compare the I/O size of the write operation request with write data size ranges corresponding to the granularities of the logical addresses of the plurality of types of FTLs, where the write data size ranges corresponding to the granularities of the logical addresses of the FTLs are different. An FTL corresponding to a write data size range that the I/O size of the write operation request meets is used as the target FTL.) store the data in the flash memory portion; ([Zhou abstract, 0057, 0060, Figs. 1, 2] After receiving a write operation request, the flash device selects a target FTL from the FTLs based on the received write operation request and allocates a physical address from the flash device to the received write operation request based on the target FTL. The management module 203 is configured to allocate a physical address from the flash device to the received write operation request based on the selected target FTL. the management module 203 is configured to allocate the physical address from the flash device to the write operation request based on a granularity of a flash physical address mapped by the target FTL.) and map the data in the FTL using the indirection unit size ([Zhou abstract, 011. 0061, Fig. 2] each of the FTLs records a mapping from a logical address to a flash physical address. the flash device 200 further includes a recording module 204. The recording module 204 is configured to, after the physical address is allocated to the write operation request, record, in the target FTL, a mapping relationship between the logical address of the write operation request and the physical address allocated from the flash device. allocating a physical address from the flash device to the write operation request based on the target FTL may include allocating the physical address from the flash device to the write operation request based on a granularity of a flash physical address mapped by the target FTL. The granularity of the flash physical address mapped by the target FTL may be a fine granularity, for example, a 512-byte or 1-kilobyte (KB) mapping granularity, or may be a coarse granularity, for example, a 4-KB or 8-KB mapping granularity. An FTL mapping granularity may be an integer multiple of a sector size (a typical value is 512 bytes). In this possible implementation, the physical address is allocated from the flash device based on FTLs with different granularities, so that storage space in the flash device is properly allocated by using the FTLs with different granularities.).
Zhou does not explicitly disclose wherein the FTL is configured to accommodate multiple indirection unit sizes.
Peterson teaches wherein the FTL is configured to accommodate multiple indirection unit sizes ([Peterson 0019, 0024, 0030] These logical-to-physical mappings are described in indirection units stored in the indirection mapping table. An indirection manager 216 can enable indirection units in the indirection mapping table to be stored, modified, or updated. For example, the size of the journal can be made equal to the size of an indirection unit such that the journal can be written in a single write operation and the next journal can include entries starting with the next indirection unit. Since each journal is stored at a predetermined location, each journal includes entries that map a fixed amount of physical media to logical units. Where these logical units are of fixed size, each journal has a fixed number of journal entries. If the logical units are of variable sizes, e.g., where compression is used, journals are still stored at predetermined locations. Embodiments described above assume that each indirection entry corresponds to a fixed amount of disk space such that after a particular number of entries (e.g., the size of the journal) the journal is stored at a predetermined location. However, where compression algorithms are used, each entry may not correspond to the same amount of disk space. As such, if the journal is of fixed size and it is stored when it is filled, it may not be stored at a predetermined location. In some embodiments, a variable sized journal may be used that can be stored to disk upon detection that data has been written up to a predetermined location.).
Zhou and Peterson are analogous art because they are from the same field of endeavor in storage devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhou and Peterson before him or her to modify the flash device management module of Zhou to include the variable sized indirection units of Peterson, thereafter the flash device management module is connected to the variable sized indirection units. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the flash device management module have more ability to vary the size of the indirection unit as suggested by Peterson. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Zhou with Peterson to obtain the invention as specified in the instant application claims.
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 2, 10, and 18, taking claim 2 as exemplary, Zhou in view of Peterson teaches
The storage device of claim 1, wherein the information associated with the one or more requests comprises an indication of the indirection unit size that is received from the storage system controller ([Zhou 0010-0011] if the target FTL is selected based on the I/O size of the write operation request, the following manner may be used: separately comparing the I/O size of the write operation request with write data size ranges corresponding to the granularities of the logical addresses of the plurality of types of FTLs, where the write data size ranges corresponding to the granularities of the logical addresses of the FTLs are different, and using, as the target FTL, an FTL corresponding to a write data size range that the I/O size of the write operation request meets. It should be understood that a write data size range may be set based on a granularity of a logical address of an FTL, and the granularity is a storage space size. In this possible implementation, the write data size ranges corresponding to the granularities of the logical addresses of the plurality of types of FTLs are set, and the target FTL is selected based on the set write data size ranges, to implement an implementation in which the target FTL is selected based on the I/O size of the write operation request. In this implementation, rationality and accuracy of the target FTL may be improved. allocating a physical address from the flash device to the write operation request based on the target FTL may include allocating the physical address from the flash device to the write operation request based on a granularity of a flash physical address mapped by the target FTL. The granularity of the flash physical address mapped by the target FTL may be a fine granularity, for example, a 512-byte or 1-kilobyte (KB) mapping granularity, or may be a coarse granularity, for example, a 4-KB or 8-KB mapping granularity. An FTL mapping granularity may be an integer multiple of a sector size (a typical value is 512 bytes). In this possible implementation, the physical address is allocated from the flash device based on FTLs with different granularities, so that storage space in the flash device is properly allocated by using the FTLs with different granularities.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 3, 11, and 19, taking claim 3 as exemplary, Zhou in view of Peterson teaches
The storage device of claim 1, wherein the information associated with the one or more requests comprises a logical address for storing the data, wherein the logical address falls within a range of logical addresses that are allocated to use the indirection unit size ([Zhou 0010, 0012] if the target FTL is selected based on the I/O size of the write operation request, the following manner may be used: separately comparing the I/O size of the write operation request with write data size ranges corresponding to the granularities of the logical addresses of the plurality of types of FTLs, where the write data size ranges corresponding to the granularities of the logical addresses of the FTLs are different, and using, as the target FTL, an FTL corresponding to a write data size range that the I/O size of the write operation request meets. It should be understood that a write data size range may be set based on a granularity of a logical address of an FTL, and the granularity is a storage space size. In this possible implementation, the write data size ranges corresponding to the granularities of the logical addresses of the plurality of types of FTLs are set, and the target FTL is selected based on the set write data size ranges, to implement an implementation in which the target FTL is selected based on the I/O size of the write operation request. In this implementation, rationality and accuracy of the target FTL may be improved. the data storage method may further include, after the physical address is allocated to the write operation request, recording, in the target FTL, a mapping relationship between the logical address of the write operation request and the physical address allocated from the flash device. The logical address may be a logical block address (LBA), and the physical address may be a physical page address (PPA). In this possible implementation, the mapping relationship between the logical address of the write operation request and the physical address allocated from the flash device is recorded in the target FTL, so that when an access request for accessing the logical address is received next time, a corresponding physical address may be quickly queried, to implement a quick response to the access request.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 4, 12, and 20, taking claim 4 as exemplary, Zhou in view of Peterson teaches
The storage device of claim 1, wherein the indirection unit size is selected based on a type of the data ([Zhou 0009] selecting a target FTL from the plurality of types of FTLs based on the received write operation request may include selecting the target FTL from the plurality of types of FTLs based on at least one of an input/output (I/O) size of the write operation request, a data type carried in the write operation request, a service type for sending the write operation request, or modification frequency of data in a logical address corresponding to the write operation request. In this possible implementation, the I/O size of the write operation request, the data type carried in the write operation request, the service type for sending the write operation request, or the modification frequency of the data in the logical address corresponding to the write operation request are used as a basis for selecting the target FTL. A suitable target FTL may be more accurately selected for the write operation request, to implement proper allocation of a physical address of the flash device and maximize capacity space of the flash device.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 5 and 13, taking claim 5 as exemplary, Zhou in view of Peterson teaches
The storage device of claim 1, wherein the storage device controller is configured to map a plurality of data stored in the flash memory portion using two or more indirection unit sizes accommodated through the FTL ([Zhou 0031-0032, 0038] if the granularity of the logical address of the FTL is 4 KB, a size of a logical block corresponding to one FTL mapping unit or FTL mapping entry is 4 KB, and one FTL mapping entry occupies 32-bit (that is, 4 bytes) memory space in a memory. Correspondingly, the granularity of the logical address of the FTL may alternatively be 512 bytes, 8 KB, 16 KB, or the like. In this embodiment of this application, the granularity of the logical address of the FTL may be an integer multiple of a sector size (for example, 512 bytes). For FTLs with logical addresses of different granularities, a larger granularity of a logical address of an FTL indicates a larger logical block, fewer FTL mapping entries, and smaller occupied memory space. A smaller granularity of a logical address of an FTL indicates a smaller logical block, more FTL mapping entries, and larger occupied memory space. For example, granularities of logical addresses of FTLs are respectively 4 KB and 8 KB. If written data is 16 KB, and the FTL with the logical address whose granularity is 4 KB is used, four FTL mapping entries are required for mapping. For example, one FTL mapping entry is 32 bits. In this case, memory space correspondingly occupied by the written data is 128 bits.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 8 and 16, taking claim 8 as exemplary, Zhou in view of Peterson teaches
The storage device of claim 1, wherein the storage device is a managed flash storage device ([Zhou abstract, 0057, Fig. 2] data storage method in a flash device and a flash device, where the flash device includes a plurality of flash translation layers (FTLs). A flash device 200 includes a receiving module 201, a selection module 202, and a management module 203. The management module 203 is configured to allocate a physical address from the flash device to the received write operation request based on the selected target FTL.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Claim(s) 6-7 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 20220129189 A1) in view of Peterson (US 20180095680 A1) as applied to claims 1 and 9 above, and further in view of Frolikov (US 20220129189 A1).
Referring to claims 6 and 14, taking claim 6 as exemplary, Zhou in view of Peterson teaches
The storage device of claim 1 (see above).
Zhou in view of Peterson does not explicitly disclose wherein the storage device controller is further configured to: reallocate one or more blocks of the flash memory portion that are mapped using a first indirection unit size in the FTL to use a different indirection unit size in the FTL, wherein the flash memory portion has remaining blocks mapped to the first indirection unit size. Zhou does teach the I/O size of the write operation request is separately compared with write data size ranges corresponding to the granularities of the logical addresses of the plurality of types of FTLs, where the write data size ranges corresponding to the granularities of the logical addresses of the FTLs are different. An FTL corresponding to a write data size range that the I/O size of the write operation request meets is used as the target FTL ([Zhou 0038-0039]). Peterson further teaches variable sizing and indirection implemented as various data structures, where each indirection entry may represent multiple logically and contiguous data blocks ([Peterson 0019, 0024, 0030].
Frolikov teaches wherein the storage device controller is further configured to: reallocate one or more blocks of the flash memory portion that are mapped using a first indirection unit size in the FTL to use a different indirection unit size in the FTL ([Frolikov 0076, 0235-0245, Fig. 19] The administrative manager (225) receives commands (e.g., 261, 263, 265) from the host (e.g., 101 in FIG. 1) to create (261), delete (263), or change (265) a namespace (e.g., 221 or 223). In response, the administrative manager (225) generates/updates a namespace map (255), such as the namespace map (273) to implement the mapping illustrated in FIG. 2 or 9. A namespace (e.g., 221 or 223) may be changed to expand or shrink its size (e.g., by allocating more blocks for the namespace, or returning some of its blocks to the pool of free blocks). In general, changing the block size may increase the number of partial blocks in the updated namespace map of an existing namespace, from no more than one, to more than one. FIG. 19 illustrates block size changes for namespace mapping including decreasing (451) from the large block size (133) to the small block size (132) and increasing (453) from the small block size (132) to the large block size (133).) wherein the flash memory portion has remaining blocks mapped to the first indirection unit size ([Frolikov 0101, 0209 Figs. 7, 11, 17] In FIG. 7, the portion (113) of the full block (127) (or partial block (113)) is allocated for the namespace (111); and the remaining portion (115) of the full block (127) (or partial block (115)) is not allocated for the namespace (111). The remaining portion (115), or a portion of it, can be subsequently allocated to another namespace that also needs a partial block. Different namespaces may use different portions (e.g., 113, 115) of the full block (127). At block 1711, the first partial block is selected and allocated to the namespace. In one example, partial block (1501) is allocated. In one example, the partial block having portions (1601), (1603) is allocated. In one example, the namespace is over-provisioned by allocating both portions (1601), (1603) to the namespace. In an alternative example, remaining portion (1603) is retained in the free block pool as part of a partial block available for allocation to another namespace.).
Zhou, Peterson, and Frolikov are analogous art because they are from the same field of endeavor in storage devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhou, Peterson, and Frolikov before him or her to modify the flash device management module of Zhou and Peterson to include the administrative management of Frolikov, thereafter the flash device management module is connected to the administrative management. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the flash device management module have more ability to expand or shrink the size of the namespace (i.e. indirection unit) as suggested by Frolikov. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Zhou and Peterson with Frolikov to obtain the invention as specified in the instant application claims.
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 7 and 15, taking claim 7 as exemplary, Zhou in view of Peterson and Frolikov teaches
The storage device of claim 6, wherein the one or more blocks of the flash memory portion are reallocated while avoiding moving data stored at the one or more blocks of the flash memory portion ([Frolikov 0076, 0235-0245, Fig. 19] When the capacity (220) is divided according to the large block size (133), the namespace (221) in FIG. 19 is mapped to a set of full large L-blocks (233 and 239). Since the set of logical addresses in the full large L-blocks (223 and 239) is the same as the set of logical addresses in the full small L-blocks (463, 464, 467 and 468), the namespace map of the namespace (221) can be simply updated, from mapping to full large L-blocks (233 and 239), to mapping to full small L-blocks (463, 464, 467 and 468) to implement the block size decrease (451). Similarly, to implement the block size increase (453), the namespace map of the namespace (221) can be simply updated, from mapping to full small L-blocks (463, 464, 467 and 468), to mapping to full large L-blocks (233 and 239).).
The same motivation that was utilized for combining Zhou, Peterson, and Frolikov as set forth in claim(s) 6 and 14 is equally applicable to this/these claim(s).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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