DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 09/26/2024 for application number 18/897,791. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, IDS, and Certified Copy of Foreign Priority Application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
Claims 1 and 6-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, and 6 of Copending Application No. 18/898,652 in view of SOLIMAN et al., US 2017/0308148 A1.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Although the claims at issue are not identical, the differences are highlighted below:
Instant Application
18/898,652
An information processing apparatus comprising:
a computer system; and
a power supply circuit,
wherein the power supply circuit is configured to supply power supplied from an external power source or a battery to the computer system,
the computer system is configured to switch a system state among a normal state, a first low power state, and a second low power state,
The first low power state is a state in which power consumption is lower than power consumption in the normal state,
The second low power state is a state in which power consumption is lower than the power consumption in the first low power state, and
The computer system is configured to
change the system state to the second low power state
when the system state is the first low power state and an actual measurement value of power consumption is greater than a predetermined reference value.
An information processing apparatus comprising:
a computer system; and
a power supply circuit,
wherein the power supply circuit is configured to supply power supplied from an external power source or a battery to the computer system,
the computer system is configured to switch a system state among a normal state, a first low power state, and a second low power state,
the first low power state is a state in which power consumption is lower than the power consumption in the normal state,
the second low power state is a state in which power consumption is lower than the power consumption in the first low power state, and
the computer system is configured to
determine a setting value for a decrease in remaining capacity such that the setting value increases as the remaining capacity of the battery increases when starting the first low power state, and
change the system state to the second low power state
when the first low power state continues until a decrease amount from the remaining capacity at the start of the first low power state reaches the setting value.
The information processing apparatus according to claim 1,
wherein the first low power state is modern standby,
and the second low power state is hibernation.
The information processing apparatus according to claim 1,
wherein the first low power state is a modern standby,
and the second low power state is hibernation.
A control method for an information processing apparatus including a power supply circuit configured to supply power supplied from an external power source or a battery to a computer system,
in which the computer system is configured to switch a system state among a normal state, a first low power state, and a second low power state, the first low power state is a state in which power consumption is lower than power consumption in the normal state, the second low power state is a state in which power
consumption is lower than the power consumption in the first low power state, the control method comprising causing the information processing apparatus to execute:
a step of changing the system state to the second low power state when the system state is the first low power state and an actual measurement value of power consumption is greater than a predetermined reference value.
A control method for an information processing apparatus including a computer system, and a power supply circuit configured to supply power supplied from an external power source or a battery to the computer system,
in which the computer system is configured to switch a system state among a normal state, a first low power state, and a second low power state, the first low power state is a state in which power consumption is lower than power consumption in the normal state, and the second low power state is a state in which power consumption is lower than the power consumption in the first low power state, the control method comprising causing the information processing apparatus to execute:
a step of determining a setting value for a decrease in remaining capacity such that the setting value increases as the remaining capacity of the battery increases when starting the first low power state; and
a step of changing the system state to the second low power state when the first low power state continues until a decrease amount from the remaining capacity at the start of the first low power state reaches the setting value.
Claim 1 of the instant application and Claim 1 of the ‘652 copending application are both directed towards transitioning from a first low power state to a second low power state. However, Claim 1 of the ‘652 application does not explicitly teach the condition to change when the system state is the first low power state and an actual measurement value of power consumption is greater than a predetermined reference value.
SOLIMAN teaches when the system state is the first low power state and an actual measurement value of power consumption is greater than a predetermined reference value (Fig. 5, blocks 502-503 disclose detecting the computing device is in standby state (i.e. system state is in the first low power state) then obtaining drain rate data; [0041] discloses when the observed drain rate (i.e. the actual measurement value of power consumption) exceeds the ideal drain rate (i.e. is greater than a predetermined reference value) the system drops to hibernate).
It would have been obvious to one of ordinary skill in the art, having the teachings of the ‘652 copending application and SOLIMAN before him before the effective filing date of the claimed invention, to incorporate the transition based on ideal drain rate and observed drain rate as taught by SOLIMAN, into the information processing apparatus as disclosed by the ‘652 copending application to strike a good balance between performance and battery life (SOLIMAN [0002]).
Claim 7 of the instant application recites limitations similar to those of Claim 1 of the instant application, and is rejected accordingly.
Claim 6 of the instant application depends on Claim 1, and corresponds to Claim 4 of the ‘652 copending application, and is rejected accordingly.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by SOLIMAN et al., US 2017/0308148 A1.
Regarding Claim 1, SOLIMAN discloses:
An information processing apparatus (Fig. 2, computing device 200)
comprising: a computer system (computing device 102);
a power supply circuit (energy storage device system 128),
wherein the power supply circuit is configured to supply power supplied from an external power source or a battery to the computer system ([0016] discloses the energy storage device system 128 (i.e. the power supply circuit) having one or multiple energy storage devices (e.g., batteries) (i.e. a battery to the computer system)),
the computer system is configured to switch a system state among a normal state, a first low power state, and a second low power state ([0017] discloses the hibernate engine 127 in the computing device 102 (i.e. a component in the computer system) may be implemented to control (i.e. is configured) when to transition between device states (i.e. switch a system state) such as active (i.e. a normal state), standby (i.e. a first low power state), and hibernate (i.e. a second low power state)),
the first low power state is a state in which power consumption is lower than power consumption in the normal state ([0019] discloses the active state (i.e. the normal state) may be associated with moderate utilization whereas the standby state (i.e. the first low power state) is a low-power state used to conserve power to reduce power consumption (i.e. power consumption is lower than power consumption in the normal state)),
the second low power state is a state in which power consumption is lower than the power consumption in the first low power state ([0019] discloses the hibernate (i.e. the second low power state) represents an even deeper power conservation state and power usage is less than the standby state (i.e. power consumption is lower than the power consumption in the first low power state)),
and the computer system is configured to change the system state to the second low power state when the system state is the first low power state and an actual measurement value of power consumption is greater than a predetermined value ([0052-0053] disclose the computing device 102 is configured to (i.e. the computer system is configured to) switch to a hibernate state (i.e. switch to the second low power state) after detecting the device is in standby state (i.e. when the system state is the first low power state). A switch to a hibernate state implemented by the power management scheme is selectively triggered based on the observed drain rate and a policy established for transitions between the standby state and the hibernate state; [0041] discloses when the observed drain rate (i.e. the actual measurement value of power consumption) exceeds the ideal drain rate (i.e. is greater than a predetermined reference value) the system drops to hibernate).
Regarding Claim 7, HARIHARAN discloses:
A control method for an information processing apparatus (Fig. 5 discloses a procedure (i.e. control method) for the computing device 200 (i.e. an information processing apparatus)).
The remainder of Claim 7 recites limitations similar to those of Claim 1, and is rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over SOLIMAN, in view of IMAI et al., US 2014/0201551 A1 (as cited in the IDS).
Regarding Claim 2, SOLIMAN discloses the information processing apparatus of Claim 1. While SOLIMAN discloses:
wherein the computer system is configured to determine the reference value ([0041] discloses an ideal drain rate (i.e. reference value) determined as (x%/total expected runtime)),
SOLIMAN does not explicitly disclose such that the reference value decreases as an elapsed time from start of the first low power state increase.
However, IMAI teaches such that the reference value decreases as an elapsed time from start of the first low power state increase (Fig. 7, [0074-0075] teach the power consumption P is lowered to the start power Pst at time t0 to start power idle state (i.e. the first low power state); A line 183 (i.e. the reference value) represents the reference value at P1 and lowers (i.e. decreases) to the lower limit value Pil in the elapsed time t from the t0 start of the power idle state (i.e. from the start of the first low power state increase)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of SOLIMAN and IMAI before him before the effective filing date of the claimed invention, to incorporate a decreasing reference value over time as taught by IMAI into the computing device as disclosed by SOLIMAN, to provide a method of balancing ability to quickly resume and reduction of power consumption (IMAI [0020]).
Regarding Claim 5, SOLIMAN discloses the information processing apparatus of Claim 1. While SOLIMAN discloses:
the reference value for the power consumption ([0041] discloses the ideal drain rate),
SOLIMAN does not explicitly disclose wherein the reference value for the power consumption is greater than a standard value of the power consumption in the first low power state.
However, IMAI teaches wherein the reference value for the power consumption is greater than a standard value of the power consumption in the first low power state ([0070] teaches a reference value 177 (i.e. the reference value for the power consumption) that includes an upper limit value Pih and lower limit value Pil of the power idle state (i.e. in the first low power state); [0071] teaches the average power consumption Pav (i.e. a standard value of the power consumption) lies between the upper limit Pih and the lower limit Pil (i.e. the reference value is greater than the standard value)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of SOLIMAN and IMAI before him before the effective filing date of the claimed invention, to incorporate a reference value greater than a standard value as taught by IMAI into the computing device as disclosed by SOLIMAN, to give priority to quickly resume to power-on state (IMAI [0016]).
Claims 3-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over SOLIMAN, in view of HSIA et al., US 2023/0114256 A1.
Regarding Claim 3, SOLIMAN discloses the information processing apparatus of Claim 1. While SOLIMAN discloses:
Wherein the computer system is configured to determine the actual measurement value of the power consumption ([0021] discloses monitoring (i.e. determining) the observed drain rate (i.e. the actual measurement value of the power consumption),
SOLIMAN does not explicitly disclose determining the actual measurement value of the power consumption based on a remaining capacity of the battery at a plurality of time points.
However, HSIA teaches determining the actual measurement value of the power consumption based on a remaining capacity of the battery at a plurality of time points ([0011] teaches the remaining capacity of the power source (i.e. remaining capacity of the battery) may be monitored at regular time intervals (i.e. at a plurality of time points)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of SOLIMAN and HSIA before him before the effective filing date of the claimed invention, to incorporate monitoring the remaining capacity at different time intervals as taught by HSIA into the computing device as disclosed by SOLIMAN, to reduce the power consumption of the computing device (HSIA [0010]).
Regarding Claim 4, SOLIMAN and HSIA disclose the information processing apparatus of Claim 3. SOLIMAN further discloses:
Wherein the computer system is configured to determine the actual measurement value of the power consumption based on an elapsed time from start of the first low power state ([0039-0040] disclose the observed drain rate (i.e. the actual measurement value of the power consumption) is monitored (i.e. determine) when in standby (i.e. based on the elapsed time from the start of the first low power state)),
And a decrease amount in remaining capacity of the battery from the start of the first low power state ([0039-0040] disclose the observed drain rate is based on a rate at which power available via the energy storage system is being utilized (i.e. a decrease amount in remaining capacity of the battery) when monitored in standby (i.e. from the start of the first low power state)).
Regarding Claim 6, SOLIMAN discloses the information processing apparatus of Claim 1. SOLIMAN further discloses:
the second low power state is hibernation ([0019] discloses the hibernate (i.e. the second low power state is hibernation) represents an even deeper power conservation state).
While SOLIMAN discloses the first low power state is a standby ([0019] discloses a standby state (i.e. the first low power state) as a low-power state), SOLIMAN does not explicitly disclose wherein the first low power state modern standby.
However, HSIA teaches wherein the first low power state is a modern standby ([0020] teaches the computing device may enter a modern standby state (i.e. the first low power state is a modern standby)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of SOLIMAN and HSIA before him before the effective filing date of the claimed invention, to incorporate the modern standby state as taught by HSIA into the computing device as disclosed by SOLIMAN, to reduce the power consumption of the computing device (HSIA [0010]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Laurenz Advincula whose telephone number is (571)272-9211. The examiner can normally be reached T-F 8:30 AM - 5:30 PM EST.
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/L.A./Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
Prosecution Insights