The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
This office action has been issued in response to the response filed 5/14/26. Claims 2,4-10,13,15-22 and 24 are pending in this application. Applicant's arguments have been carefully considered, but are not persuasive in view of the “response to arguments” section below. The examiner appreciates Applicant's effort to distinguish over the cited prior art by presenting arguments/amendments in an attempt to distinguish or clarify the claimed invention, however, upon further consideration and/or search, the claims remain unpatentable over the cited prior art for the reasons articulated in the “response to arguments” section below. All claims pending in the instant application remain rejected and clarification and/or elaboration regarding why the claims are not in condition for allowance will hereafter be provided in order to efficiently further prosecution. Accordingly, this action is made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2,4-10,13,15-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang (US PGPUB # 20100332732) in view of Khmelnitsky (US PGPUB # 20090198947) further in view of Genshaft US PGPUB # 20190004941.
With respect to independent claims 2, 13, 22 Chiang/Khmelnitsky discloses: A memory system [Chiang fig 1], comprising:
one or more memory arrays [Chiang fig 1]; and
processing circuitry coupled with the one or more memory arrays [Chiang fig 1] and configured to cause the memory system to:
receive one or more commands [The interface device controls the flash memory when access to the flash memory is requested from the host … the interface device controls a read/write/erase operation of the flash memory - Chiang 0021];
update, based at least in part on the one or more commands [update mapping data based on commands – Chiang 0040-0041, fig 5a1-e], one or more mapping tables of a set of mapping tables associated with the one or more memory arrays [updating mapping tables associated with memory arrays – Chiang fig 3, 5a1-e], the one or more mapping tables each associated with a hierarchical level of two or more different hierarchical levels and comprising a correspondence between a set of logical addresses and a set of physical addresses of the one or more memory arrays [blocks are at one level of granularity and pages are at a second level of granularity where pages are smaller than blocks and blocks are comprised of pages, logical blocks/pages map only physical blocks/pages via various mapping tables – Chiang fig 5a1-e] [mapping tables each associated with a hierarchical level of two or more different hierarchical levels - Genshaft abstract, 0077-0079, fig 5, 12];
wherein the two or more different hierarchical levels comprise at least a first hierarchical level and a second hierarchical level below the first hierarchical level [hierarchical data structure 150 may include any quantity of levels that may allow and/or facilitate locating one or more physical addresses in the non-volatile memory 120, the overall hierarchical data structure 150 includes three (3) levels (e.g., L0-L2) - Genshaft abstract, 0077-0079, fig 5, 12], and wherein updating the one or more mapping tables comprises updating one or more entries of a mapping table associated with the first hierarchical level such that one or more entries of one or more mapping tables associated with the second hierarchical level that correspond to the updated one or more entries of the mapping table associated with the first hierarchical level are removed or updated based at least in part on the updating of the one or more entries of the mapping table associated with the first hierarchical level [validating a higher level range causes descendants at lower levels to be shadowed/invalidated, in other words, updating first level mapping entry and then updating/invalidating/removing corresponding second level entries – Genshaft fig 6-10 in view of paragraph 0092-0095];
transfer data from a portion of the one or more memory arrays storing the data to another portion of the one or more memory arrays [copy/merge data - Chiang 0044, 0047, claim 30, 34, fig 5g, 6c]; and
perform an erase operation on a subset of physical addresses of the set of physical addresses, the subset of physical addresses corresponding at least to the portion of the one or more memory arrays [after merge, old blocks are erased and recycled or garbage collected – Chiang 0047, 0050].
Chiang does not explicitly disclose “a hierarchical level of two or more different hierarchical levels”. Nevertheless in the same field of endeavor, Khmelnitsky teaches memory mapping techniques for non-volatile memory where logical sectors are mapped into physical pages using data structures which may be arranged in hierarchical levels of two or more different hierarchical levels (Khmelnitsky abstract, fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use data structures which may be arranged in hierarchical levels of two or more different hierarchical levels in the invention of Chiang as taught by Khmelnitsky because it would be advantageous for eliminating the need for block mapping by directly mapping logical sectors to physical pages, eliminating the need for allocating new blocks until all pages in a current block are allocated, eliminating the need for allocating different journaling blocks for different logical areas, and eliminating the need for triggering a GC operation until all pages in the current block are allocated (Khmelnitsky 0008).
Chiang/Khmelnitsky does not explicitly disclose propagating changes through a hierarchical data structure so that updates to a higher level are propagated to a lower level, claimed as “wherein updating the one or more mapping tables comprises updating one or more entries of a mapping table associated with the first hierarchical level such that one or more entries of one or more mapping tables associated with the second hierarchical level that correspond to the updated one or more entries of the mapping table associated with the first hierarchical level are removed or updated based at least in part on the updating of the one or more entries of the mapping table associated with the first hierarchical level”. Nevertheless in the same field of endeavor, Genshaft teaches validating a higher level range causes descendants at lower levels to be shadowed/invalidated, in other words, updating first level mapping entry and then updating/invalidating/removing corresponding second level entries – Genshaft fig 6-10 in view of paragraph 0092-0095
Therefore, Chiang/Khmelnitsky/Genshaft teaches all limitations of the instant claim(s).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to propagate changes through a hierarchical data structure so that updates to a higher level are propagated to a lower level in the invention of Chiang/Khmelnitsky as taught by Genshaft because it would be advantageous for decreasing the amount of time it may take to locate data in the non-volatile memory which allows the system to operate more efficiently (Genshaft 0099).
With respect to dependent claim 4, 15 Chiang/Khmelnitsky/Genshaft discloses wherein the processing circuitry is further configured to cause the memory system to: remove one or more second entries of a set of one or more mapping tables associated with the second hierarchical level of the two or more different hierarchical levels, the set of one or more mapping tables corresponding to the mapping table associated with the first hierarchical level, wherein to remove the one or more second entries is based at least in part on the update of the one or more entries of the mapping table associated with the first hierarchical level, the one or more second entries of the set of one or more mapping tables comprising a correspondence between a set of logical address and a set of physical addresses of a user portion of the one or more memory arrays storing user data [Chiang 0042-0044 fig 5b, 5d].
With respect to dependent claim 5, 16 Chiang/Khmelnitsky/Genshaft discloses wherein the set of physical addresses of the user portion of the one or more memory arrays comprise one or more contiguous addresses, wherein to update the one or more mapping tables is based at least in part on the set of physical addresses of the user portion comprising the one or more contiguous addresses [pb100-102 are contiguous and may be updated– Chiang fig 3, 5a-5g].
With respect to dependent claim 6, 17 Chiang/Khmelnitsky/Genshaft discloses wherein, to update the one or more entries of the mapping table, the processing circuitry is configured to cause the memory system to: remove at least one entry of the one or more entries, modify at least one entry of the one or more entries, or both [Chiang 0042-0044 fig 5b, 5d].
With respect to dependent claim 7, 18 Chiang/Khmelnitsky/Genshaft discloses wherein the two or more different hierarchical levels comprise at least a first granularity level, and a second granularity level, wherein the first granularity level is associated with one or more blocks or plane addresses of the one or more memory arrays, and wherein the second granularity level is associated with one or more page addresses of the one or more memory arrays [Chiang fig 3 & 5 in view of Khmelnitsky abstract, fig 1 showing hierarchical mapping data structures].
With respect to dependent claim 8, 19 Chiang/Khmelnitsky/Genshaft discloses wherein one or more memory blocks of the one or more memory arrays storing the data may be associated with an access frequency lower than a second access frequency of one or more memory blocks of the one or more memory arrays storing second data [Chiang 0030, 0053-0056, fig 7].
With respect to dependent claim 9, 20 Chiang/Khmelnitsky/Genshaft discloses wherein the processing circuitry is further configured to cause the memory system to: refrain from performing one or more garbage collection operations; replenish a pool of one or more free memory blocks of the one or more memory arrays based at least in part on one or more free memory blocks of the one or more memory arrays; and free one or more memory blocks of the portion during the transfer of the data based at least in part on the transfer of the data to the other portion [Khmelnitsky fig 3 steps 308-312].
With respect to dependent claim 10 Chiang/Khmelnitsky/Genshaft discloses wherein transferring the data is based at least in part on one or more contiguous addresses associated with the data [pb100-102 are contiguous and data therein may be transferred – Chiang fig 3, 5a-5g].
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang/Khmelnitsky/Genshaft further in view of Seo (US PGPUB # 20180225200)
With respect to dependent claim 24 Chiang/Khmelnitsky/Genshaft does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Seo teaches a nonvolatile memory system with means for selectively performing purge operations (Seo 0035). Therefor the combination of Chiang/Khmelnitsky/Genshaft/Seo discloses wherein the one or more commands comprise one or more unmap commands and a purge command, and a pattern of the one or more commands collectively indicates to the memory system to perform a reset procedure [Seo 0035, 0050 in view of fig 4, where 0035 teaches "The purge determination unit 130 may determine whether to perform a purge operation, in response to a purge request received from the external device. For example, the purge request may include a complete erase of data of the nonvolatile memory device which correspond to the unmapped logical address]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to identify a reset procedure based at least in part on one or more commands comprising a pattern of unmap commands and a purge command in the invention of Chiang/Khmelnitsky/Genshaft as taught by Seo because it would be advantageous for efficiently managing unmap and purge commands used to reset/erase a non-volatile memory while minimizing unnecessary wear on the non-volatile memory (Seo 0031 in view of 0037).
Response to Arguments
Applicant's arguments have been fully considered but are not persuasive in view of the prior art. All claims pending in the instant application remain rejected. Please note that any rejections/objection not maintained from the previous Office Action have been rectified either by applicant's amendment and/or persuasive argument(s).
Regarding applicant’s arguments on page 9-13, that amended claims are not taught by the cited art [The examiner respectfully submits that amended grounds of rejection necessitated by amendments to the claims have rendered the remarks moot/unpersuasive, particularly in view of the combination of prior art including newly found Genshaft reference as integrated into the rationale above.]
Remaining arguments are understood to be predicated on the previous arguments being persuasive and thus are unpersuasive at least on dependency merits.
All remarks are understood to have been addressed herein. If any issues remain which may be clarified by the examiner, the applicant is invited to contact the examiner to set up a telephone interview.
When responding to the office action, any new claims and/or limitations should be accompanied by a reference as to where the new claims and/or limitations are supported in the original disclosure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARWAN AYASH whose telephone number is (571)270-1179. The examiner can normally be reached 9a-730p M-R.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio del Mar Perez-Velez can be reached on 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Marwan Ayash/ - Examiner - Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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