The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Election of Group 1 (claims 2-10, 13-20) without traverse in the response filed 11/10/25 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: HIERARCHICAL MAPPING TABLES AND THRESHOLD-BASED GARBAGE COLLECTION.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-10, 13-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang (US PGPUB # 20100332732) in view of Khmelnitsky (US PGPUB # 20090198947)
With respect to independent claims 2, 13, 22 Chiang/Khmelnitsky discloses: A memory system [Chiang fig 1], comprising:
one or more memory arrays [Chiang fig 1]; and
processing circuitry coupled with the one or more memory arrays [Chiang fig 1] and configured to cause the memory system to:
receive one or more commands [The interface device controls the flash memory when access to the flash memory is requested from the host … the interface device controls a read/write/erase operation of the flash memory - Chiang 0021];
update, based at least in part on the one or more commands [update mapping data based on commands – Chiang 0040-0041, fig 5a1-e], one or more mapping tables of a set of mapping tables associated with the one or more memory arrays [updating mapping tables associated with memory arrays – Chiang fig 3, 5a1-e], the one or more mapping tables each associated with a hierarchical level of two or more different hierarchical levels and comprising a correspondence between a set of logical addresses and a set of physical addresses of the one or more memory arrays [blocks are at one level of granularity and pages are at a second level of granularity where pages are smaller than blocks and blocks are comprised of pages, logical blocks/pages map only physical blocks/pages via various mapping tables – Chiang fig 5a1-e];
transfer data from a portion of the one or more memory arrays storing the data to another portion of the one or more memory arrays [copy/merge data - Chiang 0044, 0047, claim 30, 34, fig 5g, 6c]; and
perform an erase operation on a subset of physical addresses of the set of physical addresses, the subset of physical addresses corresponding at least to the portion of the one or more memory arrays [after merge, old blocks are erased and recycled or garbage collected – Chiang 0047, 0050].
Chiang does not explicitly disclose “a hierarchical level of two or more different hierarchical levels”. Nevertheless in the same field of endeavor, Khmelnitsky teaches memory mapping techniques for non-volatile memory where logical sectors are mapped into physical pages using data structures which may be arranged in hierarchical levels of two or more different hierarchical levels (Khmelnitsky abstract, fig 1).
Therefore, Chiang/Khmelnitsky teaches all limitations of the instant claim(s).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use data structures which may be arranged in hierarchical levels of two or more different hierarchical levels in the invention of Chiang as taught by Khmelnitsky because it would be advantageous for eliminating the need for block mapping by directly mapping logical sectors to physical pages, eliminating the need for allocating new blocks until all pages in a current block are allocated, eliminating the need for allocating different journaling blocks for different logical areas, and eliminating the need for triggering a GC operation until all pages in the current block are allocated (Khmelnitsky 0008).
With respect to dependent claim 3, 14, 23 Chiang/Khmelnitsky discloses wherein, to update the one or more mapping tables of the set of mapping tables, the processing circuitry is configured to cause the memory system to: update one or more entries of a mapping table associated with a first hierarchical level of the two or more different hierarchical levels, wherein the two or more different hierarchical levels comprises at least the first hierarchical level and a second hierarchical level below the first hierarchical level [block level mapping table 331a/b operate at block level while page mapping table 332 and RW mapping table 333 operate at page level - Chiang fig 3 & 5 in view of Khmelnitsky abstract, fig 1 showing hierarchical mapping data structures].
With respect to dependent claim 4, 15 Chiang/Khmelnitsky discloses wherein the processing circuitry is further configured to cause the memory system to: remove one or more second entries of a set of one or more mapping tables associated with the second hierarchical level of the two or more different hierarchical levels, the set of one or more mapping tables corresponding to the mapping table associated with the first hierarchical level, wherein to remove the one or more second entries is based at least in part on the update of the one or more entries of the mapping table associated with the first hierarchical level, the one or more second entries of the set of one or more mapping tables comprising a correspondence between a set of logical address and a set of physical addresses of a user portion of the one or more memory arrays storing user data [Chiang 0042-0044 fig 5b, 5d].
With respect to dependent claim 5, 16 Chiang/Khmelnitsky discloses wherein the set of physical addresses of the user portion of the one or more memory arrays comprise one or more contiguous addresses, wherein to update the one or more mapping tables is based at least in part on the set of physical addresses of the user portion comprising the one or more contiguous addresses [pb100-102 are contiguous and may be updated– Chiang fig 3, 5a-5g].
With respect to dependent claim 6, 17 Chiang/Khmelnitsky discloses wherein, to update the one or more entries of the mapping table, the processing circuitry is configured to cause the memory system to: remove at least one entry of the one or more entries, modify at least one entry of the one or more entries, or both [Chiang 0042-0044 fig 5b, 5d].
With respect to dependent claim 7, 18 Chiang/Khmelnitsky discloses wherein the two or more different hierarchical levels comprise at least a first granularity level, and a second granularity level, wherein the first granularity level is associated with one or more blocks or plane addresses of the one or more memory arrays, and wherein the second granularity level is associated with one or more page addresses of the one or more memory arrays [Chiang fig 3 & 5 in view of Khmelnitsky abstract, fig 1 showing hierarchical mapping data structures].
With respect to dependent claim 8, 19 Chiang/Khmelnitsky discloses wherein one or more memory blocks of the one or more memory arrays storing the data may be associated with an access frequency lower than a second access frequency of one or more memory blocks of the one or more memory arrays storing second data [Chiang 0030, 0053-0056, fig 7].
With respect to dependent claim 9, 20 Chiang/Khmelnitsky discloses wherein the processing circuitry is further configured to cause the memory system to: refrain from performing one or more garbage collection operations; replenish a pool of one or more free memory blocks of the one or more memory arrays based at least in part on one or more free memory blocks of the one or more memory arrays; and free one or more memory blocks of the portion during the transfer of the data based at least in part on the transfer of the data to the other portion [Khmelnitsky fig 3 steps 308-312].
With respect to dependent claim 10 Chiang/Khmelnitsky discloses wherein transferring the data is based at least in part on one or more contiguous addresses associated with the data [pb100-102 are contiguous and data therein may be transferred – Chiang fig 3, 5a-5g].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ke US Patent # 11216381 teaches: A data storage device includes a memory device and a memory controller. The memory controller selects a predetermined memory device to receive data and accordingly records multiple logical addresses in a first mapping table. The first mapping table records which logical page the data stored in each physical page of the predetermined memory block is directed to. When the predetermined memory block is full, the memory controller edits a second mapping table and a third mapping table according to the first mapping table. The second mapping table corresponds to multiple logical pages and records which memory block and which physical page is the data of each logical page stored in. The third mapping table corresponds to the physical pages of the predetermined memory block and indicates whether each physical page is a valid page or an invalid page.
Hsu US PGPUB # 20190121726 teaches a method for accessing a flash memory module, wherein the method comprises: building a physical block recording table corresponding to a logical address to physical address (L2P) mapping table, wherein the physical block recording table records at least one block whose physical address is recorded in the L2P mapping table; and when a specific block within the flash memory module is under a garbage collection operation, for a data page of the specific block whose logical address is within the L2P mapping table, referring to the physical block recording table to determine if reading the L2P mapping table from the flash memory module or not, for determining the data page to be valid or invalid.
When responding to this Office Action, any new claims and/or limitations should be accompanied by a reference as to where the new claims and/or limitations are supported in the original disclosure.
Any inquiry concerning this communication or earlier communication from the examiner should be directed to MARWAN AYASH at (571)270-1179. The examiner may be reached via email at marwan.ayash@uspto.gov – provided that applicant files form PTO/SB/439 to authorize internet communication, found online at http://www.uspto.gov/sites/default/files/documents/sb0439.pdf
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/Marwan Ayash/
Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133