DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 6 February, 2026 has been entered. Claims 1-4, 6-12, and 15-17 remain pending in the application. Applicant’s amendments to the claims have addressed the claim interpretation concern and the rejections under 35 USC § 112 previously set forth in the Non-Final Office Action mailed 7 November, 2025. Examiner further acknowledges amendments to the claims which are rejected under 35 USC § 103 on the same grounds as the previous Action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shulkin et al (U.S. Patent Pub. No. 2019/0056994), hereinafter referred to as Shulkin.
In regard to claim 1, Shulkin teaches a storage device comprising: a memory device including a plurality of physical positions; and a memory controller configured to perform a plurality of firmware operations on at least one physical position among the plurality of physical positions (¶ 0037 the memory operates on physical units of a plurality of types e.g. physical locations; Fig. 1, ¶ 0040, lines 4-8 disclose physical memory blocks of cells; Fig. 2, ¶ 0042 discloses several controlling circuits; ¶ 0055, lines 21-28 controller may perform wear leveling, garbage collection, e.g. "firmware" operations), store position information representing a physical position at which each of the plurality of firmware operations is performed (¶ 0037, lines 1-7 disclose recording physical locations where errors are corrected (e.g. firmware operations are performed)), determine a target physical position at which a firmware operation is successively performed from among the plurality of physical positions based on the position information (¶ 0038, blocks may be targeted for wear leveling based on predicted data which is based on block FBC info, e.g. wear leveling is based on position information), and perform the firmware operation at only the target physical position among the plurality of physical positions for a predetermined time period (Fig. 21, ¶ 0158 discloses collecting FBC data (position information) during a first time period (lines 1-8) and operating only a specific subset of memory cells (e.g. a physical location) using a firmware operation in the second time period (lines 21-32)). Shulkin's disclosure also omit[s] the firmware operation at the physical positions among the plurality of physical positions other than the target physical position for the predetermined time period. Since Shulkin explicitly discloses in the cited portion that the two regions are operated differently, the firmware operation performed on the targeted subset would then functionally be omitted from the other subsets within the set of memory cells (e.g. plurality of physical locations), achieving the claimed limitation.
As for claim 2, Shulkin teaches the device of claim 1. Additionally, Shulkin teaches that the firmware operation occurs according to a physical characteristic corresponding to each of the plurality of physical positions in an operation of the memory device (¶ 0038, blocks may be targeted for wear leveling based on predicted data which is based on block FBC info, e.g. wear leveling is based on position information; ¶ 0123, lines 9-14 threshold voltages (e.g. physical characteristic) affect FBC), achieving the claimed limitation.
As for claim 6, the previously cited references teach the storage device of claim 1. Additionally, Shulkin teaches that the memory controller performs the firmware operation on at least one physical position that satisfies an occurrence condition of the firmware operation after the predetermined time period elapses. Paragraph 0037, lines 32-37 disclose that control circuits update error count data over time and ¶ 0122, lines 10-16 disclose that garbage collection may be performed in the background, which would result in continuously performing firmware operations over certain time periods as ¶ 0147, lines 15-20 disclose collecting data at various times for prediction and firmware operations in second time periods. Shulkin ¶ 0123, lines 9-17 disclose changing failed bit count probability over time results in a firmware operation of read voltage adjustment. These features allow for firmware operations to occur at a physical location based on some occurrence condition repeatedly, achieving the claimed limitation.
As for claim 7, the previously cited references teach the storage device of claim 1. Additionally, Shulkin teaches that the memory controller re-determines the target physical position, based on a firmware operation performed after the predetermined time period elapses. Paragraph 0147, lines 15-20 disclose collecting data at various times for prediction and firmware operations in second time periods, e.g. data is functionally collected after a prediction period elapses for updating predictions. Paragraph 0037 discloses that failed bit counts are collected when data is corrected by ECC (e.g. undergoes a firmware operation) and ¶ 0123, lines 9-17 disclose changing failed bit count probability over time results in a firmware operation of read voltage adjustment at a determined physical location, achieving the claimed limitation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 9-11, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Shulkin in view of Ma et al (U.S. Patent Pub. No. 2020/0110708), hereinafter referred to as Ma.
In regard to claim 3, the previously cited references teach the storage device of claim 1. They do not teach the remaining limitations of claim 3. However, Ma teaches an embodiment wherein, at the target physical position, a number of times the firmware operation is successively performed exceeds a predetermined number of times. Paragraph 0070 discloses targeting a memory page for error detection, and ¶ 0072 discloses targeting based on a number of error correction operations performed meeting or exceeding a predetermined value. Paragraph 0074 discloses this results in targeting the block containing the page for a read reclaim (e.g. firmware) operation. If combined with the block targeting of Shulkin referenced in the rejection of claim 1, the claimed limitation is achieved. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Ma in order to target memory locations with high error correction rates and to benefit from a more stable read reclaim operation (¶ 0006 discloses prevention of decreased read speed and prevention of data loss) which includes the limitations of claim 3.
As for claim 9, applicant is directed to the rejection of claim 3, as the independent claim 1 and the dependent claim 3 include the same limitations as claim 9, and are therefore rejected on the same rationale.
As for claim 10, applicant is directed to the rejection of claim 3, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 11, the previously cited references teach the device of claim 9, including performing a firmware operation according to a number of firmware operations performed. Additionally, in the combination cited in the rejection of claim 6, firmware operations happen continuously under a condition unrelated to a number of times that a firmware operation is performed, meaning that when the number of times the firmware operation is performed does not reach the predetermined number of times, the memory controller performs the firmware operation on at least one physical position satisfying an occurrence condition of the firmware operation among the plurality of physical positions, so the limitation is an expected outcome of the combination in the rationale of rejected claim 6.
As for claim 15, applicant is directed to the rejection of claim 3, as the independent claim 1 and the dependent claim 3 include the same limitations as claim 15, and are therefore rejected on the same rationale.
As for claim 16, applicant is directed to the rejection of claim 3, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 17, the previously cited references teach the method of claim 15. Additionally, the rationale for rejection of claim 3 addresses the limitation of performing a firmware operation at a physical location determined based on a reference value-based number of firmware operations performed, and the rationale for rejection of claim 7 addresses re-determining and continuously performing firmware operations, meaning the cited references achieve the claimed limitation of determining a target physical position based on a firmware operation being performed there a second number of times.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shulkin in view of Ma and Rothberg (U.S. Patent Pub. No. 2017/0068468).
In regard to claim 4, the previously cited references teach the storage device of claim 3. They do not teach the remaining limitations of claim 4. However, Rothberg teaches a method for decreasing operating parameters as device lifetime decreases (¶ 0033, lines 12-15 life values are assigned to memory blocks e.g. physical positions; ¶ 0035, devices with a shorter lifetime have operating parameters reduced to extend life). If combined with the predetermined error correction operation count disclosed by Ma, a person of ordinary skill in the art would arrive at the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Ma in order to more aggressively error correct memory locations based on a reducing memory lifetime (as reduced memory lifetime typically results in greater error occurrence as known in the art) and optimize operating parameters based on projected life (¶ 0003) which can increase performance or extend flash memory lifetimes (¶ 0035, lines 14-21).
As for claim 12, applicant is directed to the rejection of claim 4, as the claims include the same limitations and are therefore rejected on the same rationale.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shulkin in view of Lin et al ("On Harmonizing Data Lifetime and Block Retention Time for Flash devices", 2018), hereinafter referred to as Lin. The previously cited references teach the device of claim 1. They do not explicitly teach the remaining limitations of claim 8. However, Lin discloses a data organization structure wherein data retention time of a block is reduced as P/E cycles increase e.g. as lifetime decreases (Lin part III § A, ¶ 2; Table I). When combined with the firmware operation time periods disclosed by Shulkin ¶ 0158 which can be continuously selected to achieve different operation time periods according to ¶ 0155, decreased drive lifetime would result in reduced time periods spent operating on a specified physical location (as different operations in other physical locations would be required as more physical locations require refreshing due to reduced data retention periods), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Lin in order to perform firmware operations (refreshes) at different locations more frequently as lifetime decreases and increases the need for defect management, as well as "eliminate unnecessary and avoidable data refreshing and/or data migrations without degrading the device endurance" (Lin part II § B, ¶ 2, lines 8-10).
Response to Arguments
Applicant's arguments filed 6 February, 2026 (see page 7 of response) have been fully considered but they are not persuasive.
Arguments with respect to the limitations of canceled claims 5 and 13-14 which have been included in amended claims 1 and 9, respectively (see pages 7-8 of response), were unpersuasive. Shulkin's disclosure as cited teaches that a specified subset of cells is operated differently from other cells in a set, such operations including garbage collection. Additionally, Shulkin's disclosure of targeted firmware operations explicitly discloses embodiments where only one block is targeted for firmware operations in the second time period, as in ¶ 0160, ¶ 0162, ¶ 0164 using "block(s)", ¶ 0163 specifies "a block", ¶ 0165 discloses targeting "one or more" bad blocks. This would lead a person of ordinary skill in the art to arrive at the claimed limitations as a matter of functional implementation of Shulkin's disclosure, wherein only a single block could be targeted for a “firmware operation” in the period after the disclosed data collection period.
Applicant's statement that claim 1 is "directed to a count of the number of times the firmware operation is performed successively" (see page 8 of response) is reading additional limitations into the claim, as claim 1 (as amended) does not include a count of any kind as currently amended, only a limitation that blocks are targeted for successive (i.e. next) operations based on position information. Applicant's similar statement for claim 15 (see page 9) also reads additional limitations into claim 15, as the count utilized in the claim has no relation to successive or consecutive operations as currently amended.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/ Examiner, Art Unit 2139
/REGINALD G BRAGDON/ Supervisory Patent Examiner, Art Unit 2139