DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kalyanam et al (US Patent 10860051).
Regarding claim 1, Figure 2B of Kalyanam discloses an apparatus comprising:
a processing engine [Figure 1A; column 5 lines 30-35]
a digital filter coupled to the processing engine, the digital filter configured to model a power delivery network (PDN) for voltage overshoot mitigation for the processing engine [230; column 8 lines 50-55; column 9 lines 25-30]
a controller coupled to the digital filter, the controller configured to transfer a plurality of digital filter parameters to the digital filter [299; column 10 lines 50-60]
Regarding claim 2, Figure 2B of Kalyanam discloses a table of instructions to be executed by the processing engine to generate a plurality of energy estimates for the digital filter [column 6 lines 15-35].
Regarding claim 3, Figure 2B of Kalyanam discloses wherein the digital filter is further configured to generate a predicted voltage output based on the plurality of energy estimates [column 9 lines 15-55].
Regarding claim 4, Figure 2B of Kalyanam discloses a proactive voltage overshoot mitigation (PVM) module comprising of the digital filter, the PVM module configured to generate a voltage overshoot control signal based on the predicted voltage output [column 9 lines 15-55].
Regarding claim 5, Figure 2B of Kalyanam discloses wherein the PVM module is further configured to apply the voltage overshoot control signal to the processing engine [column 9 lines 15-55].
Regarding claim 6, Figure 2B of Kalyanam discloses an apparatus comprising:
means for configuring a digital filter to model a power delivery network (PDN) for voltage overshoot mitigation for a processing engine [Figure 1A; column 5 lines 30-35; 230; column 8 lines 50-55; column 9 lines 25-30]
means for configuring a plurality of energy estimates for the digital filter [230; column 8 lines 50-55; column 9 lines 25-30]
means for generating a predicted voltage output based on the plurality of energy estimates [299; column 10 lines 50-60]
Regarding claim 7, Figure 2B of Kalyanam discloses wherein the digital filter is a second order digital infinite impulse response (IIR) bandpass filter [column 8 lines 50-60].
Regarding claim 8, Figure 2B of Kalyanam discloses means for generating a voltage overshoot control signal based on the predicted voltage output to adapt instruction issue control; and means for applying the voltage overshoot control signal to the processing engine [column 9 lines 15-55].
Regarding claim 9, Figure 2B of Kalyanam discloses means for transferring a plurality of digital filter parameters when configuring the digital filter, and wherein the plurality of digital filter parameters depends on filter coefficients [column 9 lines 15-55].
Regarding claim 10, Figure 2B of Kalyanam discloses means for generating the plurality of energy estimates from an instruction issue sequence, and wherein the plurality of energy estimates is a plurality of energy per clock cycle estimates [column 9 lines 15-55].
Regarding claim 11, Figure 2B of Kalyanam discloses a method comprising:
configuring a digital filter to model a power delivery network (PDN) for voltage overshoot mitigation for a processing engine [Figure 1A; column 5 lines 30-35; 230; column 8 lines 50-55; column 9 lines 25-30]
configuring with a plurality of energy estimates for the digital filter [230; column 8 lines 50-55; column 9 lines 25-30]
generating a predicted voltage output based on the plurality of energy estimates [299; column 10 lines 50-60]
Regarding claim 12, Figure 2B of Kalyanam discloses wherein the digital filter is an Nth order digital infinite impulse response (IIR) bandpass filter [column 8 lines 50-60].
Regarding claim 13, Figure 2B of Kalyanam discloses wherein the digital filter is a second order digital infinite impulse response (IIR) bandpass filter [column 8 lines 50-60].
Regarding claim 14, Figure 2B of Kalyanam discloses transferring a plurality of digital filter parameters when configuring the digital filter [column 9 lines 15-55].
Regarding claim 15, Figure 2B of Kalyanam discloses wherein the plurality of digital filter parameters depends on filter coefficients [column 9 lines 15-55].
Regarding claim 16, Figure 2B of Kalyanam discloses generating a voltage overshoot control signal based on the predicted voltage output to adapt instruction issue control [column 9 lines 15-55].
Regarding claim 17, Figure 2B of Kalyanam discloses applying the voltage overshoot control signal to the processing engine [column 9 lines 15-55].
Regarding claim 18, Figure 2B of Kalyanam discloses wherein the plurality of energy estimates is a plurality of energy per cycle per clock cycle estimates [column 7 lines 45-67 and column 8 lines 1-10].
Regarding claim 19, Figure 2B of Kalyanam discloses wherein the plurality of energy estimates is a plurality of maximum energy per cycle per clock cycle estimates [column 7 lines 45-67 and column 8 lines 1-10].
Regarding claim 20, Figure 2B of Kalyanam discloses generating the plurality of energy estimates from an instruction issue sequence [column 7 lines 45-67 and column 8 lines 1-10].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TOMI SKIBINSKI/Primary Examiner, Art Unit 2836
Prosecution Insights