DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I, claims 1-7 and 13-16 in the reply filed on 15 June 2026 is acknowledged. Because applicant did not distinctly and specifically point out any supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.[claims 5 and 7 – “a result output from the comparison circuit”]
Claim 1 recites (emphasis added):
1. A device including a plurality of pixels, each of the plurality of pixels comprising: …
a first switch arranged between the counting circuit and the first memory; and
a comparison circuit connected to the counting circuit and the first memory,
wherein the first switch switches between connection and disconnection between the counting circuit and the first memory according to a detection signal that is based on a signal output from the comparison circuit.
Claim 5 recites (emphasis added):
5. The device according to claim 1,
wherein each of the plurality of pixels further comprises a processing circuit connected to the comparison circuit, and
wherein the detection signal is a signal which is output from the processing circuit according to a result output from the comparison circuit.
Claim 7 recites (emphasis added):
7. The device according to claim 1, wherein, in a case where a result output from the comparison circuit is less than or equal to a predetermined threshold value, the first memory does not output a signal.
It is unclear whether “a signal output from the comparison circuit” and “a result output from the comparison circuit” are to be considered the same signal, or whether they are two separate and distinct signals.
Since only one signal line is present between the comparison circuit 214 and processing circuit 215 (see e.g. Figure 1) and the specification does not appear to describe two separate signals being output from the comparison circuit (e.g. Paragraph 0069), “a signal output from the comparison circuit” and “a result output from the comparison circuit” will be read as the same signal.
Clarification is required.
Allowable Subject Matter
Claims 1-4, 6 and 13-16 are allowed.
Claims 5 and 7 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.[claims 1-7 and 13-16]
Regarding claims 1-7 and 13-16, the prior art does not teach or reasonably suggest a device including a plurality of pixels, each of the plurality of pixels comprising:
an avalanche photodiode;
a counting circuit configured to count a number of photons which have entered the avalanche photodiode within an exposure period;
a first memory connected to the counting circuit;
a first switch arranged between the counting circuit and the first memory; and
a comparison circuit connected to the counting circuit and the first memory,
wherein the first switch switches between connection and disconnection between the counting circuit and the first memory according to a detection signal that is based on a signal output from the comparison circuit.
While the prior art teaches similar systems variously including an avalanche photodiode, a counting circuit, a memory, a switch and a comparison circuit, the prior art does not teach or reasonably suggest the particular features recited in claims 1-7 and 13-16.
For example, Mikajiri et al. ((S 2023/0217137 A1) teaches an image sensor comprising a plurality of pixels (Figure 1), each including an avalanche photodiode (Figure 3, 22), a counter (Figure 1, 342) and a comparison circuit (Figure 1, 344). However, Mikajiri does not teach a memory and a switch as required.
Zhu et al. (US 2022/0155153 A1) teaches an image sensor including pixels each including a counter and comparison circuit (Figure 1, 11; Figure 24, 112h and 1133) which outputs a signal to cause a memory to store a value (Figure 1, WRen signal causing memory 13 to store value of time code generating unit 12). However, Zhu does not teach a switch which switches between connection and disconnection between the counting circuit and the first memory according to a detection signal that is based on a signal output from the comparison circuit as required.
Numata (US 2022/0120610 A1) teaches an image sensor comprising pixels each including a counter (Figure 5, 211 or 212), a comparison circuit (Figure 5, 213) and a memory which stores information of a second counter (Figure 5, 212) in response to a comparison of a signal of a first counter exceeding a threshold (Figure 5, 213 comparing output of 211; Paragraph 0032). However, Numata does not teach a first switch or wherein the first switch switches between connection and disconnection between the counting circuit and the first memory according to a detection signal that is based on a signal output from the comparison circuit as required.
Ryoki et al. (US 2021/0123802 A1) teaches an image sensor comprising pixels each including a counter, a first switch and a memory wherein the switch switches between a connection and disconnection between the counter and the memory (Figure 1, counter 114 connected to memory 116 via switch 115). However the switch switches in accordance with a control signal WRT from timing generator TG 102 and not a comparison circuit as required.
Hikosaka (US 2023/0224609 A1) teaches a pixel including first and second counters which are connected by a switch (Figure 4, counters 32 and 34 connected by MUX SEL2), but does not teach a memory or comparison circuit as required.
Kobayashi et al. (US 2019/0068908 A1 – Figure 1) and Suzuki et al. (US 2020/0252569 A1 – Figure 3) teach similar systems having pixel counters and memories, but also do not teach the particular requirements of the claims including a first switch, wherein the first switch switches between connection and disconnection between the counting circuit and the first memory according to a detection signal that is based on a signal output from the comparison circuit as required.
Therefore, while the prior art teaches similar devices, the prior art does not teach or reasonably suggest the particular requirements of claims 1-7 and 13-16. However, the above 35 USC 112(b) rejections must be overcome before all claims can be considered allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY J HENN whose telephone number is (571)272-7310. The examiner can normally be reached Monday-Friday ~10-6.
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/Timothy J Henn/ Primary Examiner, Art Unit 2639
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