DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Under MPEP 2143.03, "All words in a claim must be considered in judging the patentability of that claim against the prior art." In re Wilson, 424 F.2d 1382, 1385, 165 USPQ 494, 496 (CCPA 1970). As a general matter, the grammar and ordinary meaning of terms as understood by one having ordinary skill in the art used in a claim will dictate whether, and to what extent, the language limits the claim scope. Language that suggests or makes a feature or step optional but does not require that feature or step does not limit the scope of a claim under the broadest reasonable claim interpretation. In addition, when a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009).
Claims 2, 5-6, 11, 14-15 and 20 recite “one of.” Since “one of” is disjunctive, any one of the elements found in the prior art is sufficient to reject the claim. While citations have been provided for completeness and rapid prosecution, only one element is required. Because, on balance, it appears the disjunctive interpretation enjoys the most specification support and for that reason the disjunctive interpretation (one of A, B OR C) is being adopted for the purposes of this Office Action. Applicant’s comments and/or amendments relating to this issue are invited to clarify the claim language and the prosecution history.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 (all claims) are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by US Patent Publication 2016 0358307 A1, (Brothers et al.). References are listed in the Notice of Cited References when they were first cited. If a reference is not identifiable (e.g., due to a typo), it can be identified by searching for the quoted text.
Claim 1
Regarding Claim 1, Brothers et al. disclose a method for processing images ("rendering of graphical images in which a graphics renderer and a compute shader is utilized," paragraph [0002]), the method comprising:
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first processing of first input data at a first stage of a set of stages ("A graphics rendering engine may mix graphics operations and compute operations for many stages of post-processing and graphics calculations. In particular, without interleaving some stages of processing generate intermediate results that may be written to memory ( e.g., external memory) and read back later to generate the next intermediate or final resulting image," paragraph [0040]), the first processing being performed with a first data access mode to generate first output data ("the data access pattern of image load/store operations in the compute shader(s) are analyzed to determine if they are candidates for interleaving," paragraph [0022] where a pattern is a mode);
transforming the first output data to a second format associated with a second data access mode to generate second input data for a second stage of the set of stages ("support is provided in the driver 108 and a compiler (not illustrated) to automatically convert compute shader(s) to operate with a tiled access pattern by converting a compute shader to a tiled version in module 140," paragraph [0024]); and
processing the second input data at the second stage according to the second data access mode ("A graphics renderer processes pixels, vertices, patches, or primitives," paragraph [0019]).
Claim 2
Regarding Claim 2, Brothers et al. disclose the method of claim 1, wherein the first data access mode includes one of a column-major processing order, a row-major processing order ("if the data access pattern is a statically known strided pattern in 1D or 2D space, the compute shader is a candidate for interleaving," paragraph [0022]), a tiled order, or a zigzag processing order.
Claim 3
Regarding Claim 3, Brothers et al. disclose the method of claim 1, further comprising automatically detecting the first data access mode of the first stage and the second data access mode of the second stage ("the graphics system automatically (e.g., without human intervention) interleaves the processing of graphics rendering and compute shaders in order to reduce or eliminate writing and reading intermediate data to the external (off-chip) memory," paragraph [0026] where automatically interleaving requires detecting a first (graphics rendering) mode or a second (compute shader) mode).
Claim 4
Regarding Claim 4, Brothers et al. disclose the method of claim 3, wherein the automatically detecting is performed by a compiler analyzing patterns of accesses of code of the first stage and code of the second stage ("a determination of when interleaving is allowed is based on an analysis of memory access patterns of image load/store operations in the compute shader at compilation time. If the memory access pattern is statically-known strided pattern in ID or 2D space, then the compute shader is a candidate for interleaving," paragraph [0033]).
Claim 5
Regarding Claim 5, Brothers et al. disclose the method of claim 1, further comprising maintaining one or more of registers, cache, or memory between the first stage and the second stage ("the interleaved scheduling module 130 schedules the interleaved execution of each tile. The output of a graphics renderer for a given tile is stored in on-chip memory 160 (or, e.g., other on chip storage such as a data register or buffer)," paragraph [0036]).
Claim 6
Regarding Claim 6, Brothers et al. disclose the method of claim 1, wherein the transforming is performed by instructions of the first stage, the second stage, or both the first stage and the second stage ("A graphics rendering engine may mix graphics operations and compute operations for many stages of post-processing and graphics calculations. In particular, without interleaving some stages of processing generate intermediate results that may be written to memory ( e.g., external memory) and read back later to generate the next intermediate or final resulting image," paragraph [0040]).
Claim 7
Regarding Claim 7, Brothers et al. disclose the method of claim 1, wherein the transforming is performed as a hardware accelerated operation ("As used herein, a module can correspond to a hardware component, a software component, or a combination thereof. For example, a module can include one or more processors (e.g., computer processors) and a data storage device including program instruction," paragraph [0043]).
Claim 8
Regarding Claim 8, Brothers et al. disclose the method of claim 1, wherein the transforming comprises copying the first input data from a first location to a second location in a way that adjusts positions of elements of the first input data to match an access pattern of the second access mode ("compute shader might generate a position of particles, and only a particle affecting a specific XY region is of interest for the graphics renderer," paragraph [0032]).
Claim 9
Regarding Claim 9, Brothers et al. disclose the method of claim 1, wherein the transforming comprises copying edge pixels of a tile format to generate the second input data ("This may include recompiling, using the compiler, the compute shader to adapt the compute shader to perform a tiled memory access in a tile format compatible with that of the tiled memory access of a graphics renderer. In one embodiment, this includes redefining the workgroup dimension of the compute shader to be an integer divisor of a tile's width and height," paragraph [0024] where redefining the dimension includes copying edge pixels).
Claim 10
Regarding Claim 10, Brothers et al. disclose a system for processing images("rendering of graphical images in which a graphics renderer and a compute shader is utilized," paragraph [0002]), the system comprising:
a memory configured to store first input data("some stages of processing generate intermediate results that may be written to memory ( e.g., external memory) and read back later to generate the next intermediate or final resulting image," paragraph [0040]); and
a processor configured to ("a special purpose processor to perform one or more methods described herein," paragraph [0043]):
perform first processing of the first input data at a first stage of a set of stages ("A graphics rendering engine may mix graphics operations and compute operations for many stages of post-processing and graphics calculations. In particular, without interleaving some stages of processing generate intermediate results that may be written to memory ( e.g., external memory) and read back later to generate the next intermediate or final resulting image," paragraph [0040]), the first processing being performed with a first data access mode to generate first output data ("the data access pattern of image load/store operations in the compute shader(s) are analyzed to determine if they are candidates for interleaving," paragraph [0022] where a pattern is a mode);
transforming the first output data to a second format associated with a second data access mode to generate second input data for a second stage of the set of stages ("support is provided in the driver 108 and a compiler (not illustrated) to automatically convert compute shader(s) to operate with a tiled access pattern by converting a compute shader to a tiled version in module 140," paragraph [0024]); and
processing the second input data at the second stage according to the second data access mode ("A graphics renderer processes pixels, vertices, patches, or primitives," paragraph [0019]).
Claim 11
Regarding Claim 11, Brothers et al. disclose the system of claim 10, wherein the first data access mode includes one of a column-major processing order, a row-major processing order ("if the data access pattern is a statically known strided pattern in 1D or 2D space, the compute shader is a candidate for interleaving," paragraph [0022]), a tiled order, or a zigzag processing order.
Claim 12
Regarding Claim 12, Brothers et al. disclose the system of claim 10, wherein the processor is further configured to automatically detect the first data access mode of the first stage and the second data access mode of the second stage ("the graphics system automatically (e.g., without human intervention) interleaves the processing of graphics rendering and compute shaders in order to reduce or eliminate writing and reading intermediate data to the external (off-chip) memory," paragraph [0026] where automatically interleaving requires detecting a first (graphics rendering) mode or a second (compute shader) mode).
Claim 13
Regarding Claim 13, Brothers et al. disclose the system of claim 12, wherein the automatically detecting is performed by a compiler analyzing patterns of accesses of code of the first stage and code of the second stage ("a determination of when interleaving is allowed is based on an analysis of memory access patterns of image load/store operations in the compute shader at compilation time. If the memory access pattern is statically-known strided pattern in ID or 2D space, then the compute shader is a candidate for interleaving," paragraph [0033]).
Claim 14
Regarding Claim 14, Brothers et al. disclose the system of claim 10, wherein the processor is further configured to maintain one or more of registers, cache, or memory between the first stage and the second stage ("the interleaved scheduling module 130 schedules the interleaved execution of each tile. The output of a graphics renderer for a given tile is stored in on-chip memory 160 (or, e.g., other on chip storage such as a data register or buffer)," paragraph [0036]).
Claim 15
Regarding Claim 15, Brothers et al. disclose the system of claim 10, wherein the transforming is performed by instructions of the first stage, the second stage, or both the first stage and the second stage ("A graphics rendering engine may mix graphics operations and compute operations for many stages of post-processing and graphics calculations. In particular, without interleaving some stages of processing generate intermediate results that may be written to memory ( e.g., external memory) and read back later to generate the next intermediate or final resulting image," paragraph [0040]).
Claim 16
Regarding Claim 16, Brothers et al. disclose the system of claim 10, wherein the transforming is performed as a hardware accelerated operation ("As used herein, a module can correspond to a hardware component, a software component, or a combination thereof. For example, a module can include one or more processors (e.g., computer processors) and a data storage device including program instruction," paragraph [0043]).
Claim 17
Regarding Claim 17, Brothers et al. disclose the system of claim 10, wherein the transforming comprises copying the first input data from a first location to a second location in a way that adjusts positions of elements of the first input data to match an access pattern of the second access mode ("compute shader might generate a position of particles, and only a particle affecting a specific XY region is of interest for the graphics renderer," paragraph [0032]).
Claim 18
Regarding Claim 18, Brothers et al. disclose the system of claim 10, wherein the transforming comprises copying edge pixels of a tile format to generate the second input data ("This may include recompiling, using the compiler, the compute shader to adapt the compute shader to perform a tiled memory access in a tile format compatible with that of the tiled memory access of a graphics renderer. In one embodiment, this includes redefining the workgroup dimension of the compute shader to be an integer divisor of a tile's width and height," paragraph [0024] where redefining the dimension includes copying edge pixels).
Claim 19
Regarding Claim 19, Brothers et al. disclose a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations ("rendering of graphical images in which a graphics renderer and a compute shader is utilized," paragraph [0002]) comprising:
first processing of first input data at a first stage of a set of stages ("A graphics rendering engine may mix graphics operations and compute operations for many stages of post-processing and graphics calculations. In particular, without interleaving some stages of processing generate intermediate results that may be written to memory ( e.g., external memory) and read back later to generate the next intermediate or final resulting image," paragraph [0040]), the first processing being performed with a first data access mode to generate first output data ("the data access pattern of image load/store operations in the compute shader(s) are analyzed to determine if they are candidates for interleaving," paragraph [0022] where a pattern is a mode);
transforming the first output data to a second format associated with a second data access mode to generate second input data for a second stage of the set of stages ("support is provided in the driver 108 and a compiler (not illustrated) to automatically convert compute shader(s) to operate with a tiled access pattern by converting a compute shader to a tiled version in module 140," paragraph [0024]); and
processing the second input data at the second stage according to the second data access mode ("A graphics renderer processes pixels, vertices, patches, or primitives," paragraph [0019]).
Claim 20
Regarding Claim 20, Brothers et al. disclose the non-transitory computer-readable medium of claim 19, wherein the first data access mode includes one of a column-major processing order, a row-major processing order ("if the data access pattern is a statically known strided pattern in 1D or 2D space, the compute shader is a candidate for interleaving," paragraph [0022]), a tiled order, or a zigzag processing order.
Reference Cited
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
US Patent Publication 2025 0308130 A1 to Pathak et al. discloses distributing primitives to a set of screen space processors based on a first assignment configuration; modifying assignment configuration to replace the first assignment configuration with a second assignment configuration; and distributing primitives to the set of screen space processors based on the second assignment configuration.
US Patent Publication 2022 0222771 A1 to Berger et al. discloses a multidirectional rolling cache to store image data
US Patent Publication 2020 0402263 A1 to Larson et al. discloses compressor to compress image data from a row-and-column format into nonoverlapping tiles including blocks of pixels, a processor to write the blocks of pixels one tile at a time in a column-wise manner across an image strip to create image data, and an on-chip memory to store the image data.
Conclusion
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/Heath E. Wells/Examiner, Art Unit 2664
Date: 11 August 2026
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