DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because it does not meet with the require length (should be a single paragraph within the range of 50 to 150 words in length). Correction is required. See MPEP § 608.01(b).
Drawings
The drawings are objected to because Figure 3 label “S42”, which should be “S14” (see Specification; paragraph [0046]). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because upper structure of Figure 9 label “424,22”, which should be “42,422” (see Specification; paragraph [0056]). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because lower structure of Figure 11 label “4,4202”, which should be “42,420”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 2 is objected to because of the following informalities: Claim 2, line 3 recites “all the switches (S1,S2,S3)”, which should be -- all the switches (S1,S2,S3, S4)— based on the previously switches presented in the claim.
Appropriate correction is required.
Claim 5 is objected to because of the following informalities: Claim 5, line 8 recites “first DC voltage terminal element (42)”, which should be -- first DC voltage terminal element (40)— based on Figure 9, part 40,400.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9, 12 and 13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Nakamura et al. (US 2016/0219689), hereinafter Nakamura.
Regarding claim 1, Nakamura discloses (see figures 1-11) a three-level power semiconductor module (1) (figure 6B, part 10/4a) (paragraph [0031]; FIG. 2 is a circuit diagram which illustrates an example of the structure of a three-level inverter), comprising: a housing (2) (figure 5, part 40), with a switching device (3) (figure 6B, part switching device inside of 10/4a; regarding figure 2, part switching device at 4 and 5), with a first, a second and a third DC voltage terminal element (40, 42, 44) (figures 2 and 6B, parts P, M and N) which form a group (figure 6B, part 30), and with an AC voltage terminal element (50) (figures 2 and 6B, part U) (paragraph [0074]); the switching device (3) (figure 6B, part switching device inside of 10/4a; regarding figure 2, part switching device at 4 and 5) has a normal direction (N) (figure 6B, part normal direction [top view]) and is in the form of a TNPC circuit arrangement (figure 2), which has a DC branch with an upper first switch (S1) (figure 2, part Q1) whose power input (figure 2, part Q1; upper input) is connected to a high potential (DCP) of a DC voltage source (figure 2, part P), with a lower fourth switch (S4) (figure 2, part Q2) whose power output (figure 2, part Q2; output) is connected to a low potential (DCM) of a DC voltage source (figure 2, part N) and with a center tap (AC) (figure 2, part U) and a T branch (figure 2, part T branch generated by 5) with a second switch (S2) (figure 2, part Q12) whose power input (figure 2, part Q12; input) is connected indirectly or directly to an intermediate potential (DCN) (figure 2, part M) and with a third switch (S3) (figure 2, part Q11), connected in series with the second switch (S2) (figure 2, part Q12), whose power input (figure 2, part Q11; input) is connected indirectly or directly to the center tap (AC) (figure 2, part U); wherein the focal points (S11, S41) of the first and fourth switch (S1, S4) (figure 2, parts Q1 and Q2) (figure 6B, part focal points of Q1 and Q2 inside of 4a; see figure 4A, part focal points of 14 and 16 at straight line 41) lie in the direction from the group of DC voltage terminals (40, 42, 44) (figure 6B, part 30) to the AC voltage terminal (50) (figures 2 and 6B, part U) on a first straight line (G1) (figures 4A and 6B, part first straight line 41 at 4a); and the focal points (S21, S31) of the second and third switch (S2, S3) (figure 2, parts Q12 and Q11) (figure 6B, part focal points of Q12 and Q11 inside of 10; see figure 4A, part focal points of 14 and 16 at straight line 41) lie in the direction from the group of DC voltage terminals (40, 42, 44) (figure 6B, part 30) to the AC voltage terminal (50) (figures 2 and 6B, part U) on a second straight line (G2) (figures 4A and 6B, part second straight line 41 at 10) adjacent to the first straight line (figures 4A and 6B, part first straight line 41 at 4a) (paragraph [0072]-[0077]).
Regarding claim 2, Nakamura discloses everything claimed as applied above (see claim 1). Further, Nakamura discloses (see figures 1-11) the current-carrying capacity of all the switches (S1, S2, S3) is identical (figure 9, parts Q1, Q2, Q22 and Q21).
Regarding claim 3, Nakamura discloses everything claimed as applied above (see claim 1). Further, Nakamura discloses (see figures 1-11) each said respective switch (S1, S2, S3, S4) (figure 2, parts Q1, Q2, Q12 and Q11) is in the form of a power semiconductor component or a group of power semiconductor components connected in parallel (figure 2, parts Q1, Q2, Q12 and Q11); wherein the respective power semiconductor component (figure 2, parts Q1, Q2, Q12 and Q11) is in the form of at least one of an IGBT, an IGBT with antiparallel-connected diodes, a MOS-FET, a SiC-MOS-FET, an HEMT, and a GaN-HEMT (figure 2, parts Q1, Q2, Q12 and Q11).
Regarding claim 4, Nakamura discloses everything claimed as applied above (see claim 1). Further, Nakamura discloses (see figures 1-11) each of the respective focal points (S11, S21, S31, S41) (figure 2, parts Q1 and Q2) (figure 6B, part focal points of Q1 and Q2 inside of 4a; see figure 4A, part focal points of 14 and 16 at straight line 41) and (figure 2, parts Q12 and Q11) (figure 6B, part focal points of Q12 and Q11 inside of 10; see figure 4A, part focal points of 14 and 16 at straight line 41) form the corners of a trapezoid or a parallelogram (figure 6B, part form the corners of the focal points in 4a and 10; as rectangle shape).
Regarding claim 9, Nakamura discloses everything claimed as applied above (see claim 1). Further, Nakamura discloses (see figures 1-11) each of the connection surfaces (400, 420, 440) (figures 6B, parts 30a-30d) lie next to one another, not in series (figures 6B, parts 30a-30d), and in projection in the normal direction (N) (figures 6B, parts 30a-30d; in projection in the normal direction [top view]).
Regarding claim 12, Nakamura discloses everything claimed as applied above (see claim 1). Further, Nakamura discloses (see figures 1-11) each of the DC voltage terminal elements (40, 42, 44) (figures 2 and 6B, parts P, M and N) are arranged on a first narrow side (20) (figures 5 and 6B, part narrow side at P, M and N) of the housing (2) (figure 5, part 40).
Regarding claim 13, Nakamura discloses everything claimed as applied above (see claim 1). Further, Nakamura discloses (see figures 1-11) the AC voltage terminal element (50) (figures 2 and 6B, part U) is arranged on a second narrow side (22) (figures 5 and 6B, part narrow side at U) of the housing (2) (figure 5, part 40).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US 2016/0219689), hereinafter Nakamura, in view of Kobolla et al. (US 2019/0020285), hereinafter Kobolla.
Regarding claim 14, Nakamura discloses everything claimed as applied above (see claim 1). Further, Nakamura discloses (see figures 1-11) the switching device (figure 6B, part switching device inside of 10/4a; regarding figure 2, part switching device at 4 and 5). However, Nakamura does not expressly disclose a centrally arranged fastening cut-out (6) extends through the switching device.
Kobolla teaches (see figures 1-7) a centrally arranged fastening cut-out (6) (figure 6, part centrally arranged fastening cut-out at 92) extends through the switching device (figure 6, part switching device 4) (paragraph [0056]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the three-level power semiconductor module of Nakamura with the centrally arranged fastening cut-out features as taught by Kobolla, because it provides more efficient module construction that relieves the tensile loading of the terminal elements (paragraph [0009]).
Claims 5-8, 10, 11 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US 2016/0219689), hereinafter Nakamura, in view of Steger et al. (US 2021/0336553), hereinafter Steger.
Regarding claim 5, Nakamura discloses everything claimed as applied above (see claim 1). Further, Nakamura discloses (see figures 1-11) each of the respective connection surfaces (400, 420, 440) (figures 6B, parts 30a-30d) of the DC voltage terminal elements (40, 42, 44) (figures 2 and 6B, parts P, M and N) has an identical normal direction (N) and are arranged next to one another in projection in the normal direction (N) (figures 6B, parts 30a-30d; in projection in the normal direction [top view]); and wherein the third connection surface (440) (figure 6B, part 30d) of the third DC voltage terminal element (44) (figures 2 and 6B, part N) and the first connection surface (400) (figure 6B, part 30a) of the first DC voltage terminal element (42) (figures 2 and 6B, part P). However, Nakamura does not expressly disclose the third connection surface (440) of the third DC voltage terminal element (44) lies in a first plane (E1) and the first connection surface (400) of the first DC voltage terminal element (42) lies in a second plane (E2) parallel to the first when viewed in the normal direction (N).
Steger teaches (see figures 1-4)the third connection surface (440) of the third DC voltage terminal element (44) (figures 1 and 2, part 52) lies in a first plane (E1) (figures 1 and 2, part upper first plane) and the first connection surface (400) of the first DC voltage terminal element (42) (figures 1 and 2, part 50) lies in a second plane (E2) (figures 1 and 2, part lower second plane) parallel to the first when viewed in the normal direction (N) (figures 1 and 2, part upper first plane) (paragraphs [0025]-[0029]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the each of the respective connection surfaces of the DC voltage terminal elements of Nakamura with the connection surfaces of the DC voltage terminal elements features as taught by Steger and obtain each of the respective connection surfaces (400, 420, 440) of the DC voltage terminal elements (40, 42, 44) has an identical normal direction (N) and are arranged next to one another in projection in the normal direction (N); and wherein the third connection surface (440) of the third DC voltage terminal element (44) lies in a first plane (E1) and the first connection surface (400) of the first DC voltage terminal element (42) lies in a second plane (E2) parallel to the first when viewed in the normal direction (N), because it provides more efficient connection and space arrangement that enables very low inductances on the direct current (DC) voltage side (paragraph [0026]).
Regarding claim 6, Nakamura and Steger teach everything claimed as applied above (see claim 5). Further, Nakamura discloses (see figures 1-11) the second connection surface (420) (figures 6B, part 30c) of the second DC voltage terminal element (42) (figures 6B, part M) when viewed in the normal direction (N) (figure 6B, part normal direction [top view]). However, Nakamura does not expressly disclose lies in the second plane (E2) when viewed in the normal direction (N).
Steger teaches (see figures 1-4) the connection surface (420) of the DC voltage terminal element (figures 1 and 2, part 50) lies in the second plane (E2) when viewed in the normal direction (N) (figures 1 and 2, part lower second plane).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the second connection surface of the DC voltage terminal element of Nakamura with the connection surfaces of the DC voltage terminal elements features as taught by Steger and obtain the second connection surface (420) of the second DC voltage terminal element (42) lies in the second plane (E2) when viewed in the normal direction (N), because it provides more efficient connection and space arrangement that enables very low inductances on the direct current (DC) voltage side (paragraph [0026]).
Regarding claim 7, Nakamura and Steger teach everything claimed as applied above (see claim 5). Further, Nakamura discloses (see figures 1-11) the first DC voltage terminal element (40) (figures 2 and 6B, part P) is connected to the high potential (DCP) (figure 2, part P); the second DC voltage terminal element (42) (figures 2 and 6B, part M) is connected to the intermediate potential (DCN) (figure 2, part M); and the third DC voltage terminal element (44) (figures 2 and 6B, part N) is connected to the low potential (DCM) (figure 2, part N).
Regarding claim 8, Nakamura and Steger teach everything claimed as applied above (see claim 5). Further, Nakamura discloses (see figures 1-11) the first DC voltage terminal element (40) (figures 2 and 6B, part N) is connected to the low potential (DCM) (figure 2, part N); the second DC voltage terminal element (42) (figures 2 and 6B, part M) is connected to the intermediate potential (DCN) (figure 2, part M); and the third DC voltage terminal element (44) (figures 2 and 6B, part P) is connected to the high potential (DCP) (figure 2, part P).
Regarding claim 10, Nakamura and Steger teach everything claimed as applied above (see claim 5). Further, Nakamura discloses (see figures 1-11) a first line section (402) (figures 2 and 6B, part first line section at 30a) of the first DC voltage terminal element (40) (figures 2 and 6B, part P) is connected directly to the first connection surface (400) (figure 6B, part 30a) and aligns at least in sections with the third connection surface (440) (figure 6B, part 30d) of the third DC voltage terminal element (44) in the normal direction (N) (figures 2 and 6B, part N).
Regarding claim 11, Nakamura and Steger teach everything claimed as applied above (see claim 5). Further, Nakamura discloses (see figures 1-11) a second line section (422) (figures 2 and 6B, part second line section at 30c) of the second DC voltage terminal element (42) (figures 2 and 6B, part M) is connected directly to the second connection surface (420) (figures 2 and 6B, part 30c) and aligns at least in sections with the third connection surface (440) (figure 6B, part 30d) of the third DC voltage terminal element (44) in the normal direction (N) (figures 2 and 6B, part N).
Regarding claim 15, Nakamura discloses everything claimed as applied above (see claim 1). Further, Nakamura discloses (see figures 1-11) a power electronics arrangement (10) (figure 6B), comprising: the three-level power semiconductor module (1) (figure 6B, part 10/4a), wherein: each of the DC voltage terminal elements (40, 42, 44) (figures 2 and 6B, parts P, M and N) of the three-level power semiconductor modules (1). However, Nakamura does not expressly disclose a plurality of three-level power semiconductor modules (1), wherein: each of the three-level power semiconductor modules (1) are arranged with their longitudinal sides (24) next to one another in a row, and each of the DC voltage terminal elements (40, 42, 44) of the each of the three-level power semiconductor modules (1) are arranged in a row.
Steger teaches (see figures 1-4) a power electronics arrangement (10) (figure 3, part 1), comprising: a plurality of power semiconductor modules (1) (figure 3, parts 2 and 4), wherein: each of the power semiconductor modules (1) (figure 3, part each of 2 and 4) are arranged with their longitudinal sides (24) next to one another in a row (figure 3, parts 2 and 4), and each of the DC voltage terminal elements (40, 42, 44) (figure 3, parts 30/32 and 50/52) of the each of the power semiconductor modules (1) (figure 3, part each of 2 and 4) are arranged in a row (figure 3, parts 30/32 and 50/52) (paragraphs [0032]-[0044]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the three-level power semiconductor module of Nakamura with the power electronics arrangement features as taught by Steger and obtain a power electronics arrangement (10), comprising: a plurality of three-level power semiconductor modules (1), wherein: each of the three-level power semiconductor modules (1) are arranged with their longitudinal sides (24) next to one another in a row, and each of the DC voltage terminal elements (40, 42, 44) of the each of the three-level power semiconductor modules (1) are arranged in a row, because it provides more robust and reliable system with more efficient connection and space arrangement that enables very low inductances on the direct current (DC) voltage side (paragraph [0026]).
Regarding claim 16, Nakamura and Steger teach everything claimed as applied above (see claim 15). Further, Nakamura discloses (see figures 1-11) each of the respective DC voltage terminal elements (40, 42, 44) (figures 2 and 6B, parts P, M and N). However, Nakamura does not expressly disclose each of the respective DC voltage terminal elements (40, 42, 44) are connected in a polarity-appropriate manner to common, respectively assigned DC voltage supply line elements (80, 82, 84) of a DC voltage supply line device (8).
Steger teaches (see figures 1-4) each of the respective DC voltage terminal elements (40, 42, 44) (figure 3, parts 30/32 and 50/52) are connected in a polarity-appropriate manner to common (figure 3, parts 30/32 and 50/52), respectively assigned DC voltage supply line elements (80, 82, 84) of a DC voltage supply line device (8) (figure 3, parts 70, 72 and 78 at 7) (paragraphs [0032]-[0044]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the three-level power semiconductor module of Nakamura with the power electronics arrangement features as taught by Steger and obtain each of the respective DC voltage terminal elements (40, 42, 44) are connected in a polarity-appropriate manner to common, respectively assigned DC voltage supply line elements (80, 82, 84) of a DC voltage supply line device (8), because it provides more robust and reliable system with more efficient connection and space arrangement that enables very low inductances on the direct current (DC) voltage side (paragraph [0026]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
Prosecution Insights