CTFR 18/898,267 CTFR 91325 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment The Amendment filed March 2, 2026 has been entered. Claims 1-20 remain pending in the application. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4, 7-11, and 14-18 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Das Sharma (US 2019/0018813) . Regarding claim 1, Das Sharma discloses: An apparatus comprising: interface circuitry to receive a memory access command ([0077] a shared memory controller (SMC) 815 can be provided that includes logic for handling load/store requests of nodes 810a-810n in the system. Load/store requests can be received by the SMC 815 over links utilizing SML and connecting the nodes 810a-810n to the SMC 815) , the memory access command identifying a memory address ([0077] shared memory data being referred to (e.g., in an instruction) by a first node according to a first address value) ; machine-readable instructions ([0159] embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element) ; and at least one processor circuit to be programmed by the machine-readable instructions to ([0159]) : identify a remote node (FIG. 8B Node F; [0082] nodes (e.g., 810f-810h) of a remote or off-board device (e.g., Device D 850d)) that maintains an association between the apparatus and at least one other node (FIG. 8B Node A) as sharing a memory region of a pooled memory (FIG. 8A/B Shared Memory 805; [0077] SMC 815 can include logic, including data structures mapping nodes' addresses to shared memory resources, to allow the SMC 815 to interpret the various access requests of the various nodes; [0077] the SMC 815 (as well as shared memory 805) can reside on a device, chip, or board separate from one or more (or even all) of the nodes 810a-810n)) , the pooled memory to include the memory address, the remote node to store an address range that corresponds to the memory region, the remote node to identify the apparatus and the at least one other node as mapped to the memory region (The claim only requires an “apparatus comprising…instructions to: identify a remote node that maintains an association between the apparatus and at least one other node as sharing a memory region of a pooled memory.” The claim does not cover the specifics of the pooled memory or the specifics of the remote node. The pooled memory and the remote node are outside the scope of the claim) ; and cause tunneling of the memory access command to the remote node ([0082] nodes (e.g., 810f-810h) of a remote or off-board device (e.g., Device D 850d)) to service the memory access command based on the association (FIG. 8B SML (shared memory link) tunnel 855; [0075] SML can be used, for instance, in communicating reads and writes of shared memory 805 (through shared memory controller 815) by the various nodes 810a-810n of a system; [0082] the SML tunnel 855 when established can operate as other SML channels and allow the nodes 810f-810h to interface with SMC 815a over SML and access shared memory 805a as any other node communicating with SMC over an SML link can) . Regarding claim 2, Das Sharma further discloses: The apparatus of claim 1, wherein one or more of the at least one processor circuit is to cause storing of an address range in a system address decoder, the address range including the memory address, the address range corresponding to a memory region mapped to the apparatus by the remote node ([0101] Translation structures (e.g., 1210a-j) can be provided to allow an SMC (e.g., 815a, 815b) to translate address values referenced by individual nodes (e.g., 810a, 810b, 810d, 810e, 810i, 810j) in their respective memory access requests from the independent node-specific address domain to global address values for the pooled memory domain. In some instances, address translation structures 1210a-j can include range registers defining translations for specific fixed ranges of the node's memory map, TLBs caching uniform page ranges of address translations, or a hybrid/combination of both; FIGs. 14 and 15) . Regarding claim 3, Das Sharma further discloses: The apparatus of claim 1, wherein the remote node is a server ([0029] A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices) and the at least one other node includes an edge node ([0029] Clients (Desktops and Mobile); [0027]) and at least one of an edge gateway server or a base station ([0029] Servers Standard and Enterprise) . Regarding claim 4, Das Sharma further discloses: The apparatus of claim 1, wherein one or more of the at least one processor circuit is to apply a cache coherency protocol to the remote node and to the at least one other node in an edge network (FIGs. 8A/8B; [0061] Protocol Layer 520a,b can provide a Coherence Protocol to support agents caching lines of data from memory) , the cache coherency protocol to be applied after the at least one other node is mapped to the memory address and after detection of an access of the memory address, the cache coherency protocol to maintain coherency of memory content between the remote node and the at least one other node ([0061] An agent wishing to cache memory data may use the coherence protocol to read the line of data to load into its cache. An agent wishing to modify a line of data in its cache may use the coherence protocol to acquire ownership of the line before modifying the data. After modifying a line, an agent may follow protocol requirements of keeping it in its cache until it either writes the line back to memory or includes the line in a response to an external request. Lastly, an agent may fulfill external requests to invalidate a line in its cache. The protocol ensures coherency of the data by dictating the rules all caching agents may follow. It also provides the means for agents without caches to coherently read and write memory data) . Regarding claim 7, Das Sharma further discloses: The apparatus of claim 1, wherein one or more of the at least one processor circuit is to cause the tunneling via a wired connection ([0080] network connections can be tunneled through to further extend access to other off-board or off-chip nodes. For instance, SML can tunnel over an Ethernet connection (e.g., provided through network controller 820) communicatively coupling the example system of FIG. 8A with another system that can also include one or more other nodes and allow these nodes to also gain access to SMC 815 and thereby shared memory 805, among other examples) for power grid edge (The phrase “for power grid edge” states the environment in which the invention can be practiced. Therefore, it is merely a statement of intended use and is not given patentable weight) . Regarding claim 8, Das Sharma discloses: At least one non-transitory machine-readable medium comprising machine-readable instructions to cause at least one processor circuit to at least ([0159] embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element) : access a dual in-line memory module (DIMM) memory access command ([0074] Shared memory 805 can be implemented utilizing synchronous dynamic random access memory (SDRAM), dual in-line memory modules (DIMM), and other non-volatile memory (or volatile memory); [0077] a shared memory controller (SMC) 815 can be provided that includes logic for handling load/store requests of nodes 810a-810n in the system. Load/store requests can be received by the SMC 815 over links utilizing SML and connecting the nodes 810a-810n to the SMC 815) , the DIMM memory access command identifying a memory address ([0077] shared memory data being referred to (e.g., in an instruction) by a first node according to a first address value) ; identify a remote node (FIG. 8B Node F; [0082] nodes (e.g., 810f-810h) of a remote or off-board device (e.g., Device D 850d)) that maintains an association between the at least one processor circuit and at least one other node (FIG. 8B Node A) as sharing a memory region of a pooled memory (FIG. 8A/B Shared Memory 805; [0077] SMC 815 can include logic, including data structures mapping nodes' addresses to shared memory resources, to allow the SMC 815 to interpret the various access requests of the various nodes; [0077] the SMC 815 (as well as shared memory 805) can reside on a device, chip, or board separate from one or more (or even all) of the nodes 810a-810n)) , the pooled memory to include the memory address, the remote node to store an address range corresponding to the memory region, the remote node to identify the at least one processor circuit and the at least one other node as mapped to the memory region (The claim only requires at “least one non-transitory machine-readable medium comprising machine-readable instructions to cause at least one processor circuit to at least: identify a remote node that maintains an association between the at least one processor circuit and at least one other node as sharing a memory region of a pooled memory.” The claim does not cover the specifics of the pooled memory or the specifics of the remote node. The pooled memory and the remote node are outside the scope of the claim) ; and cause tunneling of the DIMM memory access command to the remote node ([0082] nodes (e.g., 810f-810h) of a remote or off-board device (e.g., Device D 850d)) to service the DIMM memory access command based on the association (FIG. 8B SML (shared memory link) tunnel 855; [0075] SML can be used, for instance, in communicating reads and writes of shared memory 805 (through shared memory controller 815) by the various nodes 810a-810n of a system; [0082] the SML tunnel 855 when established can operate as other SML channels and allow the nodes 810f-810h to interface with SMC 815a over SML and access shared memory 805a as any other node communicating with SMC over an SML link can) . Regarding claim 9, Das Sharma further discloses: The at least one non-transitory machine-readable medium of claim 8, wherein the machine-readable instructions are to cause one or more of the at least one processor circuit to cause storing of an address range in a system address decoder, the address range including the memory address, the address range corresponding to a memory region mapped by the remote node to an apparatus that includes one or more of the at least one processor circuit ([0101] Translation structures (e.g., 1210a-j) can be provided to allow an SMC (e.g., 815a, 815b) to translate address values referenced by individual nodes (e.g., 810a, 810b, 810d, 810e, 810i, 810j) in their respective memory access requests from the independent node-specific address domain to global address values for the pooled memory domain. In some instances, address translation structures 1210a-j can include range registers defining translations for specific fixed ranges of the node's memory map, TLBs caching uniform page ranges of address translations, or a hybrid/combination of both; FIGs. 14 and 15) . Regarding claim 10, Das Sharma further discloses: The at least one non-transitory machine-readable medium of claim 8, wherein the remote node is a server ([0029] A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices) and the at least one other node include an edge node ([0029] Clients (Desktops and Mobile); [0027]) and at least one of an edge gateway server or a base station ([0029] Servers Standard and Enterprise) . Regarding claim 11, Das Sharma further discloses: The at least one non-transitory machine-readable medium of claim 8, wherein the machine-readable instructions are to cause one or more of the at least one processor circuit to apply a cache coherency protocol to the remote node and to the at least one other node in an edge network (FIGs. 8A/8B; [0061] Protocol Layer 520a,b can provide a Coherence Protocol to support agents caching lines of data from memory) , the cache coherency protocol to be applied after the at least one other node is mapped to the memory address and after detection of an access of the memory address, the cache coherency protocol to maintain coherency of memory content between the remote node and the at least one other node ([0061] An agent wishing to cache memory data may use the coherence protocol to read the line of data to load into its cache. An agent wishing to modify a line of data in its cache may use the coherence protocol to acquire ownership of the line before modifying the data. After modifying a line, an agent may follow protocol requirements of keeping it in its cache until it either writes the line back to memory or includes the line in a response to an external request. Lastly, an agent may fulfill external requests to invalidate a line in its cache. The protocol ensures coherency of the data by dictating the rules all caching agents may follow. It also provides the means for agents without caches to coherently read and write memory data) . Regarding claim 14, Das Sharma further discloses: The at least one non-transitory machine-readable medium of claim 8, wherein the machine-readable instructions are to cause one or more of the at least one processor circuit to cause the tunneling via a wired connection for power grid edge ([0080] network connections can be tunneled through to further extend access to other off-board or off-chip nodes. For instance, SML can tunnel over an Ethernet connection (e.g., provided through network controller 820) communicatively coupling the example system of FIG. 8A with another system that can also include one or more other nodes and allow these nodes to also gain access to SMC 815 and thereby shared memory 805, among other examples) for power grid edge (The phrase “for power grid edge” states the environment in which the invention can be practiced. Therefore, it is merely a statement of intended use and is not given patentable weight) . Regarding claim 15, Das Sharma discloses: An apparatus comprising: interface circuitry to receive a dual in-line memory module (DIMM) memory access command ([0074] Shared memory 805 can be implemented utilizing synchronous dynamic random access memory (SDRAM), dual in-line memory modules (DIMM), and other non-volatile memory (or volatile memory)) , the DIMM memory access command identifying a memory address ([0077] shared memory data being referred to (e.g., in an instruction) by a first node according to a first address value) ; and a memory controller to ([0077] a shared memory controller (SMC) 815 can be provided that includes logic for handling load/store requests of nodes 810a-810n in the system. Load/store requests can be received by the SMC 815 over links utilizing SML and connecting the nodes 810a-810n to the SMC 815) : identify a remote node (FIG. 8B Node F; [0082] nodes (e.g., 810f-810h) of a remote or off-board device (e.g., Device D 850d)) that maintains an association between the apparatus and at least one other node (FIG. 8B Node A) as sharing a memory region of a pooled memory (FIG. 8A/B Shared Memory 805; [0077] SMC 815 can include logic, including data structures mapping nodes' addresses to shared memory resources, to allow the SMC 815 to interpret the various access requests of the various nodes; [0077] the SMC 815 (as well as shared memory 805) can reside on a device, chip, or board separate from one or more (or even all) of the nodes 810a-810n)) , the pooled memory to include the memory address, the remote node to store an address range corresponding to the memory region, the remote node to identify the apparatus and the at least one other node as mapped to the memory region (The claim only requires an “apparatus comprising…a memory controller to: identify a remote node that maintains an association between the apparatus and at least one other node as sharing a memory region of a pooled memory.” The claim does not cover the specifics of the pooled memory or the specifics of the remote node. The pooled memory and the remote node are outside the scope of the claim) ; and tunnel the DIMM memory access command to the remote node ([0082] nodes (e.g., 810f-810h) of a remote or off-board device (e.g., Device D 850d)) , the DIMM memory access command to cause the remote node to service the DIMM memory access command based on the association (FIG. 8B SML (shared memory link) tunnel 855; [0075] SML can be used, for instance, in communicating reads and writes of shared memory 805 (through shared memory controller 815) by the various nodes 810a-810n of a system; [0082] the SML tunnel 855 when established can operate as other SML channels and allow the nodes 810f-810h to interface with SMC 815a over SML and access shared memory 805a as any other node communicating with SMC over an SML link can) . Regarding claim 16, Das Sharma further discloses: The apparatus of claim 15, including a system address decoder to store an address range, the address range including the memory address, the address range corresponding to a memory region mapped by the remote node to the apparatus ([0101] Translation structures (e.g., 1210a-j) can be provided to allow an SMC (e.g., 815a, 815b) to translate address values referenced by individual nodes (e.g., 810a, 810b, 810d, 810e, 810i, 810j) in their respective memory access requests from the independent node-specific address domain to global address values for the pooled memory domain. In some instances, address translation structures 1210a-j can include range registers defining translations for specific fixed ranges of the node's memory map, TLBs caching uniform page ranges of address translations, or a hybrid/combination of both; FIGs. 14 and 15) . Regarding claim 17, Das Sharma further discloses: The apparatus of claim 15, wherein the remote node is a server ([0029] A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices) and the at least one other node includes at least one of an edge gateway server or a base station ([0029] Servers Standard and Enterprise) . Regarding claim 18, Das Sharma further discloses: The apparatus of claim 15, including a coherency logic controller to apply a cache coherency protocol to the remote node and to the at least one other node (FIGs. 8A/8B; [0061] Protocol Layer 520a,b can provide a Coherence Protocol to support agents caching lines of data from memory) , the cache coherency protocol to be applied after the at least one other node is mapped to the memory address and after detection of an access of the memory address, the cache coherency protocol to maintain coherency of memory content between the remote node and the at least one other node ([0061] An agent wishing to cache memory data may use the coherence protocol to read the line of data to load into its cache. An agent wishing to modify a line of data in its cache may use the coherence protocol to acquire ownership of the line before modifying the data. After modifying a line, an agent may follow protocol requirements of keeping it in its cache until it either writes the line back to memory or includes the line in a response to an external request. Lastly, an agent may fulfill external requests to invalidate a line in its cache. The protocol ensures coherency of the data by dictating the rules all caching agents may follow. It also provides the means for agents without caches to coherently read and write memory data) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim s 5, 12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma as applied to claim 4 above, and further in view of Rose et al. (US 2019/0171573) . Regarding claim 5, Das Sharma does not appear to explicitly teach while Rose et al. discloses: The apparatus of claim 4, wherein one or more of the at least one processor circuit is to use a snoop-based coherency protocol as the cache coherency protocol ([0031] Snoop circuitry is a known type of cache coherency circuitry that can maintain an indication of which memory addresses are cached by the various caches in the system, and use that information to target snoop requests to particular caches in order to implement a cache coherency protocol) . Das Sharma and Rose et al. are analogous art because Das Sharma teach memory access between components in a computing system and Rose et al. teach cache coherency protocols. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Rose et al. before him/her, to modify the teachings of Das Sharma with the Rose et al. teachings of snoop- based cache coherency because such a modification would have amounted to little more than combining "familiar elements according to known methods" and would have been obvious because it would have done "no more than yield predictable results." (MPEP 2143 I.A.) Rose et al. teach that snoop circuitry is a known cache coherency. Implementing snooping as the cache coherency protocol would have yielded the predictable result of maintaining an indication of which memory addresses are cached by the various caches in the system and use that information to target snoop requests to particular caches. Regarding claim 12, Das Sharma does not appear to explicitly teach while Rose et al. discloses: The at least one non-transitory machine-readable medium of claim 11, wherein the machine-readable instructions are to cause one or more of the at least one processor circuit to use a snoop-based coherency protocol as the cache coherency protocol ([0031] Snoop circuitry is a known type of cache coherency circuitry that can maintain an indication of which memory addresses are cached by the various caches in the system, and use that information to target snoop requests to particular caches in order to implement a cache coherency protocol) . The motivation for combining is based on the same rational presented for rejection of claim 5. Regarding claim 19, Das Sharma does not appear to explicitly teach while Rose et al. discloses: The apparatus of claim 18, wherein the cache coherency protocol is a snoop-based coherency protocol ([0031] Snoop circuitry is a known type of cache coherency circuitry that can maintain an indication of which memory addresses are cached by the various caches in the system, and use that information to target snoop requests to particular caches in order to implement a cache coherency protocol) . The motivation for combining is based on the same rational presented for rejection of claim 5 . 07-22-aia AIA Claim s 6, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma as applied to claim 1 above, and further in view of Tsai et al. (US 11,573,839) . Regarding claim 6, Das Sharma further discloses: The apparatus of claim 1, wherein one or more of the at least one processor circuit is to cause the tunneling ([0082] an SML tunnel 855 can be established over an Ethernet, InfiniBand, or other connection coupling Device A and Device D) via a…wireless connection ([0055] A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel) . Das Sharma does not appear to explicitly teach “5G.” However, Tsai et al. disclose: 5G (FIG. 1 External Network 106 and Tunnel 140; Col 6, lines 50-60: the external network(s) 106 may include at least one public network. As used herein, the term “public network” can refer to any data communication network that can be used to convey the transmission of data between unverified entities…examples of a public network include…a 5 th Generation (5G) core network, etc.)) Das Sharma and Tsai et al. are analogous art because Das Sharma teach memory access between components in a computing system and Tsai et al. teach utilizing network resources located at edge locations. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Das Sharma and Tsai et al. before him/her, to modify the teachings of Das Sharma with the Tsai et al. teachings of tunneling via a 5G wireless network because such a modification would amount to no more than an obvious variation of the wireless communication network disclosed by Das Sharma. Regarding claim 13, Das Sharma further discloses: The at least one non-transitory machine-readable medium of claim 8, wherein the machine-readable instructions are to cause one or more of the at least one processor circuit to cause the tunneling ([0082] an SML tunnel 855 can be established over an Ethernet, InfiniBand, or other connection coupling Device A and Device D) via a…wireless connection ([0055] A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel) . Das Sharma does not appear to explicitly teach “5G.” However, Tsai et al. disclose: 5G (FIG. 1 External Network 106 and Tunnel 140; Col 6, lines 50-60: the external network(s) 106 may include at least one public network. As used herein, the term “public network” can refer to any data communication network that can be used to convey the transmission of data between unverified entities…examples of a public network include…a 5 th Generation (5G) core network, etc.)) The motivation for combining is based on the same rational presented for rejection of claim 6. Regarding claim 20, Das Sharma further discloses: The apparatus of claim 15, wherein the memory controller is to tunnel the DIMM memory access command ([0082] an SML tunnel 855 can be established over an Ethernet, InfiniBand, or other connection coupling Device A and Device D) via a…wireless connection ([0055] A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel) . Das Sharma does not appear to explicitly teach “5G.” However, Tsai et al. disclose: 5G (FIG. 1 External Network 106 and Tunnel 140; Col 6, lines 50-60: the external network(s) 106 may include at least one public network. As used herein, the term “public network” can refer to any data communication network that can be used to convey the transmission of data between unverified entities…examples of a public network include…a 5 th Generation (5G) core network, etc.)) The motivation for combining is based on the same rational presented for rejection of claim 6 . Response to Arguments 07-37 AIA Applicant's arguments filed March 2, 2026 have been fully considered but they are not persuasive. Applicant argues that Das Sharma does not disclose the amended limitations of the independent claims. The claim mapping has been updated based on applicant’s amendments. As discussed above, claim 1 only requires an “apparatus comprising…instructions to: identify a remote node that maintains an association between the apparatus and at least one other node as sharing a memory region of a pooled memory.” The claim does not cover the specifics of the pooled memory or the specifics of the remote node and therefore the prior art is not required to disclose "the remote node to store an address range that corresponds to the memory region" and "the remote node to identify the apparatus and the at least one other node as mapped to the memory region," as is set forth in claim 1. Therefore, the rejection of the independent claims as anticipated by Das Sharm is maintained. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TRACY A WARREN/ Primary Examiner, Art Unit 2137 Application/Control Number: 18/898,267 Page 2 Art Unit: 2137 Application/Control Number: 18/898,267 Page 3 Art Unit: 2137 Application/Control Number: 18/898,267 Page 4 Art Unit: 2137 Application/Control Number: 18/898,267 Page 5 Art Unit: 2137 Application/Control Number: 18/898,267 Page 6 Art Unit: 2137 Application/Control Number: 18/898,267 Page 7 Art Unit: 2137 Application/Control Number: 18/898,267 Page 8 Art Unit: 2137 Application/Control Number: 18/898,267 Page 9 Art Unit: 2137 Application/Control Number: 18/898,267 Page 10 Art Unit: 2137 Application/Control Number: 18/898,267 Page 11 Art Unit: 2137 Application/Control Number: 18/898,267 Page 12 Art Unit: 2137 Application/Control Number: 18/898,267 Page 13 Art Unit: 2137 Application/Control Number: 18/898,267 Page 14 Art Unit: 2137 Application/Control Number: 18/898,267 Page 15 Art Unit: 2137 Application/Control Number: 18/898,267 Page 16 Art Unit: 2137 Application/Control Number: 18/898,267 Page 17 Art Unit: 2137 Application/Control Number: 18/898,267 Page 18 Art Unit: 2137 Application/Control Number: 18/898,267 Page 19 Art Unit: 2137
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