DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application, which discloses and claims only subject matter disclosed in prior Application No. 17/095,689, filed 11/11/2020, appears to claim only subject matter directed to an invention that is independent and distinct from that claimed in the prior application, and names the inventor or at least one joint inventor named in the prior application. Accordingly, this application may constitute a divisional application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 7 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ryu (US 2014/0027781 A1).
Regarding claim 1, Ryu discloses a semiconductor chip (Figure 1A), comprising: a semiconductor body (Figure 1A, references 11 and 12) comprising a main surface (Figure 1A, uppermost surface of reference 12) and a rear surface (Figure 1A, lowermost surface of reference 11) opposite the main surface (Figure 1A, uppermost surface of reference 12); a first bond pad (Figure 1A, reference 22A) disposed on the main surface (Figure 1A, uppermost surface of reference 12); a second bond pad (Figure 1A, reference 24) disposed on the rear surface (Figure 1A, lowermost surface of reference 11); a first switching device (Figure 1A, reference 20A) that is monolithically integrated in the semiconductor body and comprises a first input-output terminal (Figure 1A, reference S1) that is electrically connected (paragraph 0057) to the first bond pad (Figure 1A, reference 22A); and a second switching device (Figure 1A, reference 20B) that is monolithically integrated in the semiconductor body and comprises a first input-output terminal (Figure 1A, reference S2) that is electrically connected (paragraph 0064) to the second bond pad (Figure 1A, reference 24).
Regarding claim 2, Ryu discloses the first (Figure 1A, reference 20A) and second switching devices (Figure 1A, reference 20B) form a bidirectional switch circuit (Figure 1A, reference 10A) that is connected in series between the first and second bond pads (Figure 2; paragraph 0074).
Regarding claim 3, Ryu discloses wherein the first (Figure 1A, reference 20A) and second (Figure 1A, reference 20B) switching devices each further comprise a second input-output terminal (Figure 1A, references G1 and G2), and wherein the second input-output terminals (Figure 1A, references G1 and G2) of the first (Figure 1A, reference 20A) and second (Figure 1A, reference 20B) switching devices are electrically connected to one another by an electrical connection that is internal to the semiconductor body (Fig. 7B paragraph 0091).
Regarding claim 6, Ryu discloses wherein the first (Figure 1A, reference 20A) and second (Figure 1A, reference 20B) switching devices are each configured as power transistors (paragraph 0042).
Regarding claim 7, Ryu discloses wherein the first (Figure 1A, reference 20A) and second (Figure 1A, reference 20B) switching devices are each configured as silicon carbide-based MOSFET devices or silicon carbide-based IGBTs (paragraph 0042).
Regarding claim 10, Ryu discloses wherein the first input-output terminals (Figure 1A, references S1 and S2) of the first (Figure 1A, reference 20A) and second (Figure 1A, reference 20B) switching devices are source terminals, and wherein the second input-output terminals (Figure 1A, reference 24) of the first (Figure 1A, reference 20A) and second (Figure 1A, reference 20B) switching devices are drain terminals (paragraph 0068).
Allowable Subject Matter
Claims 4, 5, 8, 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest a semiconductor chip, comprising: wherein the semiconductor chip further comprises a third bond pad disposed on the main surface and a fourth bond pad disposed on the rear surface, wherein the first switching device further comprises a control terminal that is electrically connected to the third bond pad, and wherein the second switching device further comprises a control terminal that is electrically connected to the fourth bond pad (claim 4), wherein the semiconductor chip further comprises a fifth bond pad disposed on a side surface of the semiconductor body that extends between the main and rear surfaces, and wherein the second input-output terminals of the first and second switching devices are electrically connected to the fifth bond pad (claim 5), wherein a source zone of the first switching device adjoins a silicon-terminated surface of the semiconductor body and wherein a source zone of the second switching device adjoins a carbon-terminated surface of the semiconductor body (claim 8) and wherein a source zone of the first switching device adjoins a silicon-terminated surface of the semiconductor body and wherein a source zone of the second switching device adjoins a silicon-terminated surface of the semiconductor body (claim 9), incorporated into the claims from which they depend from, further incorporated into the independent claim and in the context of its recited apparatus, along with its depending claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
September 21, 2026
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