DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 27 September 2024 has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, 5, 9-10, and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 and 9 recite that “a shortest distance between a drain terminal of the first high-potential side FET and the first switching element pair may be shorter than a shortest distance between a source terminal of the first high-potential side FET and the first switching element pair, and a shortest distance between a source terminal of the first low-potential side FET and the first switching element pair may be shorter than a shortest distance between a drain terminal of the first low-potential side FET and the first switching element pair” (emphasis added). The term “may” is permissive/optional language that fails to provide a clear indication of what is actually claimed. It is unclear whether the claim requires a specific shortest distance between components, or the claim also encompasses embodiments where the shortest distance between components is equal or longer than the listed option. Because the metes and bounds of the claim cannot be ascertained, one of ordinary skill in the art would not be reasonable apprised of the scope of the invention.
Each of Claims 3, 5, 10 and 12 recite “may” language that is permissive/optional and fails to clearly define the scope of the invention, and are therefore also rejected as being indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-10, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ide et al. (US 2022/0169011 – hereinafter Ide.)
Regarding claim 1,
Ide discloses a drive circuit board configured to output a drive signal for driving a capacitive load, comprising:
a drive circuit [50 in figs. 2, 6, and 10] configured to output the drive signal [COM in figs. 2, 6, and 10] corresponding to a base drive signal [dA in fig. 2 / aA in fig. 6; paragraph 0044-0045]; and
a wiring board [board containing circuit 50 in figs. 2, 6, and 10] provided with the drive circuit [as seen in the figures], wherein
the drive circuit includes
a first switching circuit [550 in figs. 6 and 10] including a first driver circuit [551 in figs. 6 and 10] configured to output a first drive signal [Hgs1 / Lgs1 in figs. 6 and 10] corresponding to the base drive signal and a first switching element pair [Q1 / Q2 in figs. 6 and 10] that is driven in accordance with the first drive signal to output a first switching signal [Ams1 in figs. 6 and 10; paragraphs 0049-0054],
a second switching circuit [560 in figs. 6 and 10] including a second driver circuit [562 in figs. 6 and 10] configured to output a second drive signal [Hgs2 / Lgs2 in figs. 6 and 10] corresponding to the base drive signal and a second switching element pair [Q3 / Q4 in figs. 6 and 10] that is driven in accordance with the second drive signal to output a second switching signal [AMs2 in figs. 6 and 10] corresponding to the first switching signal [paragraphs 0059-0063], and
a smoothing circuit [580 in figs. 6 and 10] configured to smooth the second switching signal and output the second switching signal thus smoothed as the drive signal [paragraphs 0067-0069],
the wiring board includes a first side and a second side located so as to be opposed to each other along a first direction [implicit and well-known that a board will have left/right sides opposite each other, and upper/lower sides opposite to each other],
the second switching element pair includes a first high-potential side FET [Q3 in figs. 6 and 10] and a first low-potential side FET [Q4 in figs. 6 and 10],
a shortest distance between a source terminal of the first high-potential side FET and the smoothing circuit is shorter than a shortest distance between a drain terminal of the first high-potential side FET and the smoothing circuit [as seen in figs. 6 and 10], and
a shortest distance between a drain terminal of the first low-potential side FET and the smoothing circuit is shorter than a shortest distance between a source terminal of the first low-potential side FET and the smoothing circuit [as seen in figs. 6 and 10.]
Regarding claim 2,
Ide further discloses wherein
a shortest distance between a drain terminal of the first high-potential side FET and the first switching element pair may be shorter than a shortest distance between a source terminal of the first high-potential side FET and the first switching element pair,
a shortest distance between a source terminal of the first low-potential side FET and the first switching element pair may be shorter than a shortest distance between a drain terminal of the first low-potential side FET and the first switching element pair [because “may be shorter” is optional language not given patentable weight, the limitation fails to distinguish over the reference; see 112 Rejection, above.]
Regarding claim 3,
Ide further discloses wherein the first switching element pair, the second switching element pair, and the smoothing circuit may be disposed along the first direction in an order of the first switching element pair, the second switching element pair, and the smoothing circuit [because “may be disposed” is optional language not given patentable weight, the limitation fails to distinguish over the reference; see 112 Rejection, above.]
Regarding claim 5,
Ide further discloses wherein
the first switching element pair may include a second high-potential side FET [Q1 in figs. 6 and 10] and a second low-potential side FET [Q2 in figs. 6 and 10],
a shortest distance between a source terminal of the second low-potential side FET and the first side may be shorter than a shortest distance between a drain terminal of the second low-potential side FET and the first side [because “may be shorter” is optional language not given patentable weight, the limitation fails to distinguish over the reference; see 112 Rejection, above],
a shortest distance between a source terminal of the second high-potential side FET and the second low-potential side FET may be shorter than a shortest distance between a drain terminal of the second high-potential side FET and the second low-potential side FET [as seen in figs. 6 and 10], and
the second low-potential side FET and the second high-potential side FET may be disposed to at least partially overlap each other when viewed from a second direction orthogonal to the first direction [the up/down direction; as seen in figs. 6 and 10.]
Regarding claim 6,
Ide further discloses wherein
the first switching circuit is configured to output the first switching signal obtained by amplifying a modulation signal based on the base drive signal, and
the second switching circuit is configured to output the second switching signal obtained by shifting a reference potential of the first switching signal based on the base drive signal [as seen in figs. 6 and 10; paragraphs 0049-0063.]
Regarding claim 7,
Ide further discloses wherein the first switching circuit includes a DA conversion circuit [510 in figs. 6 and 10] configured to convert the base drive signal into an analog base drive signal, and a modulation circuit [530 in figs. 6 and 10] configured to output the modulation signal obtained by modulating the analog base drive signal [paragraph 0045.]
Regarding claim 8,
Ide discloses a liquid ejection apparatus comprising:
a drive circuit board [10 in fig. 2] configured to output a drive signal [COM in figs. 2, 6, and 10] for driving a capacitive load [60 in fig. 2]; and
a print head [21 in figs. 2-3] configured to eject a liquid by driving the capacitive load [paragraphs 0030-0032], wherein
the drive circuit board includes
a drive circuit [50 in figs. 2, 6, and 10] configured to output the drive signal corresponding to a base drive signal [dA in fig. 2 / aA in fig. 6; paragraph 0044-0045], and
a wiring board [board containing circuit 50 in figs. 2, 6, and 10] provided with the drive circuit,
the drive circuit includes
a first switching circuit [550 in figs. 6 and 10] including a first driver circuit [551 in figs. 6 and 10] configured to output a first drive signal [Hgs1 / Lgs1 in figs. 6 and 10] corresponding to the base drive signal and a first switching element pair [Q1 / Q2 in figs. 6 and 10] that is driven in accordance with the first drive signal to output a first switching signal [Ams1 in figs. 6 and 10; paragraphs 0049-0054],
a second switching circuit [560 in figs. 6 and 10] including a second driver circuit [562 in figs. 6 and 10] configured to output a second drive signal [Hgs2 / Lgs2 in figs. 6 and 10] corresponding to the base drive signal and a second switching element pair [Q3 / Q4 in figs. 6 and 10] that is driven in accordance with the second drive signal to output a second switching signal [AMs2 in figs. 6 and 10] corresponding to the first switching signal [paragraphs 0059-0063], and
a smoothing circuit [580 in figs. 6 and 10] configured to smooth the second switching signal and output the second switching signal thus smoothed as the drive signal [paragraphs 0067-0069],
the wiring board includes a first side and a second side located so as to be opposed to each other along a first direction [implicit and well-known that a board will have left/right sides opposite each other, and upper/lower sides opposite to each other],
the second switching element pair includes a first high-potential side FET [Q3 in figs. 6 and 10] and a first low-potential side FET [Q4 in figs. 6 and 10],
a shortest distance between a source terminal of the first high-potential side FET and the smoothing circuit is shorter than a shortest distance between a drain terminal of the first high-potential side FET and the smoothing circuit [as seen in figs. 6 and 10], and
a shortest distance between a drain terminal of the first low-potential side FET and the smoothing circuit is shorter than a shortest distance between a source terminal of the first low-potential side FET and the smoothing circuit [as seen in figs. 6 and 10.]
Regarding claims 9-10 and 12-14,
These claims recite limitations substantially identical to those of Claims 2-3 and 5-7, respectively, and are therefore rejected on the same basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ide.
Regarding claims 4 and 11,
Ide discloses the claimed limitation as set forth above but fails to expressly disclose wherein a frequency of the first drive signal is higher than a frequency of the second drive signal.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a frequency of the first drive signal that is higher than a frequency of the second drive signal, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977). See also In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to optimize the frequency of the first and second drive signals for the purpose of allowing precise, high-speed switching and optimizing thermal efficiency.
Communication with the USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANNELLE M LEBRON whose telephone number is (571)272-2729. The examiner can normally be reached Monday-Friday: 9:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JANNELLE M LEBRON/ Primary Examiner, Art Unit 2853
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