Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 19 objected to because of the following informalities: claim 19, line 4: “performing calibration operation” should be amended to “performing a calibration operation”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claims 1 and 10 (and, therefore, their respective dependent claims), each claim recites, “configured to receive a clock signal from an external device” in lines 2 and 4-5 (in claim 1, for example). As claimed, it is not clear if each claimed instance of “a clock signal” should be interpreted to mean the same or different clock signals.
Referring to claims 1, 10, and 18 (and, therefore, their respective dependent claims), each claim recites or similarly recites, using claim 1 as an example, “generate a second clock signal with a varying multiplied frequency” and “generate a third clock signal by changing a frequency of the second clock signal”. As claimed, it is not clear how a second clock signal that already has a “varying” frequency is different than a third clock signal that has a “changing frequency” of the second clock signal. “Varying” and “changing” are synonyms of one another, therefore, it is not clear what makes a “third clock signal” different than a “second clock signal” as claimed.
Referring to claim 3, lines 2-3 recite, “wherein the third clock signal is a memory clock obtained by multiplying a frequency of the second clock signal”. It appears that this is intended to further limit the “generate a third clock signal by changing a frequency of the second clock signal” of claim 1, however, as claimed it is not clear if “multiplying a frequency” of claim 3 is the same as or different from the “changing a frequency” of claim 1.
Referring to claim 4, line 3 recites, “generate the third clock signal with a frequency multiplied…” The same issue as described in the rejection of claim 3 exists for claim 4 as well between “frequency multiplied…” of claim 4 and “changing a frequency” of claim 1.
Referring to claim 6, the last line recites, “configured to output the N third clock signals to the DUT”. Claim 1 recites “provide the third clock signal to a DUT”. There is a lack of clarity if the DUT receives the “third clock signal” and the “N third clock signals” or only one or the other.
Referring to claim 9, the last line recites, “provide the changed third clock signal to the DUT”. Similar to the rejection of claim 6 above, it is not clear as claimed if the DUT receives the “changed third clock signal” of claim 6 in addition to or as a replacement for the “third clock signal” provided to the DUT claimed in claim 1.
Claim 10 recites the limitation "the same" in the last line. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the clock signal" in the line 2. There is insufficient antecedent basis for this limitation in the claim since it is not clear which “a clock signal” it is referring back to in claim 10.
Referring to claims 12 and 13, the claims have the same issue being dependent on claim 10 as described in the rejections of claims 3 and 4 above.
Claim 17 recites the limitation "the PLL circuit" in the first line. There is insufficient antecedent basis for this limitation in the claim.
Referring to claim 17, the claimed “output the N third clock signals” is not clear for the same reasons as described in the rejection of claim 6 above.
Referring to claim 19, it is not clear what “the changed frequency” in lines 2-3 and “a changed frequency” in line 6 are referring back to the “varying” or “changing” of frequency claimed in claim 18 or something different.
Referring to claim 20, the claim has the same issues as explained above with a lack of clarity if the “multiplying the clock signal”, for example, is further limiting the “varying” or “changing” of frequency claimed in claim 18.
Referring to claim 20, the variables “a”, “b”, and “c” are not clearly defined. While claimed as an “integer”, it doesn’t seem to make sense that the integer could be “0” or “1”, for example.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10-15, 17, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0404417 A1 to Kim et al (herein referred to as Kim, found in Applicant’s filed IDS). In light of the 112 rejections above, the claims have been interpreted as best understood by the Examiner when applying the Kim prior art.
Referring to claim 1, Kim discloses a clock conversion device (Figure 1) comprising: a first clock generator configured to receive a clock signal from an external test device (Figure 1, test device 100) and generate a first clock signal with a fixed multiplied frequency (paragraph [0028], first clock generator 211 may generate a clock signal by increasing the frequency of an input clock signal by a fixed multiple degree); a second clock generator separated from the first clock generator and configured to receive a clock signal from the external test device and generate a second clock signal with a varying multiplied frequency (paragraph [0028], the second clock generator 212 may generate a clock signal by increasing the frequency of the input clock signal by a variable multiple degree); and a clock conversion circuit configured to: receive the second clock signal from the second clock generator, generate a third clock signal by changing a frequency of the second clock signal, and provide the third clock signal to a device under test (DUT) that is a test target (paragraphs [0031-0032], clock conversion circuit 213).
Referring to claim 2, Kim discloses wherein the first clock signal is a system clock (first clock generator 211 outputs a clock signal equivalent to a system clock), and the second clock signal is a reference clock (second clock generator 212 outputs a clock signal equivalent to a reference clock).
Referring to claim 3, Kim discloses wherein the DUT is a memory device, and wherein the third clock signal is a memory clock obtained by multiplying a frequency of the second clock signal (paragraphs [0031-0033], DUT 220).
Referring to claim 4, Kim discloses wherein the clock conversion circuit includes: a phase locked loop (PLL) circuit configured to receive the second clock signal and generate the third clock signal with a frequency multiplied with respect to the frequency of the second clock signal (paragraphs [0042-0043], PLL circuit 330, Figure 2).
Referring to claim 5, Kim discloses wherein the PLL circuit includes: a plurality of voltage controlled oscillators configured to multiply the frequency of the second clock signal by identical multiples (paragraphs [0042-0043], PLL circuit 330, Figure 2).
Referring to claim 6, Kim discloses wherein the PLL circuit further comprises: a fan-out buffer configured to expand the third clock signal to N third clock signals, wherein N is an integer of at least 2; and an output driver circuit comprising N output drivers arranged to correspond to the N third clock signals and configured to output the N third clock signals to the DUT (claim 10 & paragraph [0057]).
Referring to claim 7, Kim discloses further comprising: a calibration circuit configured to receive the first clock signal and adjust a duty ratio of the first clock signal; a test control circuit configured to receive the first clock signal and generate a test sequence control signal; and a communication circuit configured to receive the first clock signal and generate a rate change signal in response to the test sequence control signal, wherein, when the third clock signal is to be changed, the clock conversion device is configured such that communication circuit provides the rate change signal to the second clock generator (paragraphs [0041-0044], duty ratio, adjust a rising/falling slew rate = rate change & Figure 4).
Referring to claim 8, Kim discloses wherein, when the third clock signal provided to the DUT needs to be changed, the clock conversion device is configured such that the second clock generator changes the second clock signal in response to the rate change signal (paragraphs [0041-0044]).
Referring to claim 10, Kim discloses a test system comprising: a plurality of sockets on which a plurality of devices under test (DUTs) are mounted (claim 11, Figures 13A/B, sockets 722); and a clock conversion device configured to generate an output clock signal provided to the plurality of DUTs, wherein the clock conversion device comprises: a first clock generator configured to receive a clock signal from the outside and generate a first clock signal with a fixed multiplied frequency; a second clock generator separated from the first clock generator and configured to receive a clock signal from the outside and generate a second clock signal with a varying multiplied frequency; and a clock conversion circuit configured to receive the second clock signal and generate a third clock signal by changing a frequency of the second clock signal, wherein the output clock signal is the same as the third clock signal (see rejection of claim 1 above for applicable citations).
Referring to claim 11, Kim discloses further comprising: a test device including a test logic configured to generate the clock signal and control a test operation performing on the plurality of DUTs (Figure 13A, test device 710).
Referring to claim 12, Kim discloses wherein the first clock signal is a system clock, and the second clock signal is a reference clock, and wherein, when each of the plurality of DUTs is a memory device, the third clock signal is a memory clock obtained by multiplying a frequency of the second clock signal (paragraphs [0031-0033], (first clock generator 211 outputs a clock signal equivalent to a system clock), and the second clock signal is a reference clock (second clock generator 212 outputs a clock signal equivalent to a reference clock).
Referring to claim 13, Kim discloses wherein the clock conversion circuit comprises a phase locked loop (PLL) circuit configured to receive the second clock signal and generate the third clock signal with a frequency multiplied with respect to the frequency of the second clock signal (paragraphs [0042-0043], PLL circuit 330, Figure 2).
Referring to claim 14, Kim discloses wherein the clock conversion device further comprises: a calibration circuit configured to receive the first clock signal and adjust a duty ratio of the first clock signal; a test control circuit configured to receive the first clock signal and generate a test sequence control signal; and a communication circuit configured to receive the first clock signal and generate a rate change signal in response to the test sequence control signal, wherein the test system is configured such that the communication circuit provides the rate change signal to the second clock generator when a frequency of the third clock signal is changed (paragraphs [0041-0044], duty ratio, adjust a rising/falling slew rate = rate change & Figure 4).
Referring to claim 15, Kim discloses wherein, when the third clock signal provided to the plurality of DUTs needs to be changed, the test system is configured such that the clock conversion circuit changes only the second clock signal in response to the rate change signal (paragraph [0043], slew rate adjusted).
Referring to claim 17, Kim discloses wherein the PLL circuit further comprises: a fan-out buffer configured to expand the third clock signal to N third clock signals wherein N is an integer of at least 2; and an output driver circuit comprising N output drivers arranged to correspond to the N third clock signals and configured to output the N third clock signals to the plurality of DUTs (claim 10 & paragraph [0057]).
Referring to claim 18, Kim discloses a method of operating a test system including a clock conversion device configured to provide an output clock signal to a device under test (DUT), the method comprising: generating, by the clock conversion device, a first clock signal with a fixed multiplied frequency; generating, by the clock conversion device, a second clock signal with a varying multiplied frequency; generating, by the clock conversion device, a third clock signal by changing a frequency of the second clock signal; and performing a test operation by providing the third clock signal to the DUT as the output clock signal (see the rejection of claim 1 above since the limitations are similar, only in method form).
Referring to claim 20, Kim discloses wherein the generating of the first clock signal includes generating the first clock signal by multiplying a clock signal received from a test device of the test system by a times, wherein a is an integer, wherein the generating of the second clock signal includes generating the second clock signal by multiplying the clock signal by b times, wherein b is an integer different from a, and wherein the generating of the third clock signal includes generating the third clock signal by multiplying the second clock signal by c times, wherein c is an integer different from b (paragraphs [0028-0034] describe multiplying each clock signal).
Conclusion
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Justin R. Knapp
Primary Examiner
Art Unit 2112
/JUSTIN R KNAPP/Primary Examiner, Art Unit 2112
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