Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to amendment filed on 6/4/2026, claims 1 and 8 are amended, claims 1-14 are pending for examination.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected group II claims 15-20, there being no allowable generic or linking claim. Claims 15-20 need to be cancelled.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Applicant’s Arguments
Applicant’s arguments, see page 5-6, filed 6/4/2026, with respect to the rejection(s) of claim(s) 1-14 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Eichenberger et al., US 2012/0210073 A1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over HUNT et al., US 2019/0188055 A1, in view of Eichenberger et al., US 2012/0210073 A1.
Regarding claim 1, HUNT teaches a method, comprising:
determining, at a processor, that a first processor core is to access shared data (abstract; monitoring, by one or more cores of a multi-core processor, speculative instructions, where the speculative instructions store data to a shared memory location, and where a semaphore, associated with the memory location, specifies the availability of the memory location to store data; Fig.1 and section 0013); and
in response to the determining: comparing a first portion of a first cache line to a first local copy at the first processor core (section 0009-0011 and section 0018; the test-and-set operations are executed by the system by performing multiple operations. In some embodiments, these operations include a load instruction to retrieve the semaphore from memory, a compare instruction of the semaphore's value retrieved (e.g., compared to “0”), and an optional store of a value (e.g., a “1”) to the semaphore if the result of the compare is true); and
modifying a second portion of the first cache line in response to the comparing indicating a match (section 0010-0011; an optional store of a value (e.g., a “1”) to the semaphore if the result of the compare is true).
HUNT does not clearly teach modifying a second portion of a cache line different than the first portion.
However, Eichenberger teaches modifying a second portion of a cache line different than the first portion (Fig.3A-3C; Initially, a local cache memory device 305 and another local cache memory device 310 have a same cache line 330; thread 0 on a processor 0 modifies a first portion 335 in a cache line 330 in the local cache memory device 305; a thread 1 on a processor core 1 modifies a second portion 340 in the cache line 330 in a local cache memory device 310; see Fig.3B; ).
It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings Eichenberger into HUNT such as modifying a second portion of a cache line different than the first portion because this will improve performance of a parallel computing system (abstract of Eichenberge).
Regarding claims 2 and 9, HUNT teaches the first cache line stores a semaphore associated with the shared data (section 0011; when several processes running on different cores of the system are all trying to acquire the same semaphore, it is desirable to give each core a shared, read-only copy of the cache line (memory location) containing the semaphore).
Regarding claims 3 and 10, HUNT teaches the first portion comprises data indicating whether a second processor core is waiting to write to the shared data (section 0008; If the test- and set operations indicate the semaphore is set, the shared memory location is presently owned by another program thread. Accordingly, the program thread that wants access to the semaphore must wait for a specified amount of time, and then reissues the test- and set operation until the program thread is able to set the value of the semaphore, and thus take ownership of the shared memory location).
Regarding claims 4 and 11, HUNT teaches further comprising: executing a read operation for the shared data in response to the comparing indicating a match (section 0011; The test-and-set operations are executed by the system by performing multiple operations. In some embodiments, these operations include a load instruction to retrieve the semaphore from memory, a compare instruction of the semaphore's value retrieved (e.g., compared to “0”), and an optional store of a value (e.g., a “1”) to the semaphore if the result of the compare is true).
Regarding claims 5 and 12, HUNT teaches updating the second portion comprises: adjusting the second portion of the first cache line to indicate an additional reader of the shared data (section 0009; If the load operation returns a value of “0”, the semaphore is clear and can be controlled by the program thread. This is accomplished by the program thread issuing a store operation to store a value of “1” to the semaphore, thus setting and owning the semaphore. Once the semaphore is owned by the program thread, then the program thread has exclusive control of the memory location associated with that semaphore, and the program thread can manipulate the data stored in that memory location as desired. Once the program thread has finished manipulating the data at that memory location, it then issues a store operation to the semaphore to change the value to “0”, thus clearing the semaphore and allowing other program threads to access the semaphore).
Regarding claims 6 and 13, HUNT teaches the second portion of the first cache line indicates a number of processor cores that are concurrently reading the shared data (section 0007; A processor monitors instruction pointer (IP) values corresponding to speculative accesses (e.g., instructions or operations) to the semaphore, and further monitors the number of times that the speculative accesses are flushed (referred to herein as a “flush count”) from an instruction pipeline because the semaphore is set (i.e., because the shared memory location is presently owned by another program thread)).
Regarding claims 7 and 14, HUNT teaches further comprising: determining, that a second processor core is to access shared data; and in response to the determining: comparing a first portion of a second cache line to a second local copy at the second processor core; and modifying a second portion of the second cache line in response to the comparing indicating a match (it is taught by claim 1, as shown in Fig.1; a multi-core processor 102 having four processor cores, referred to as cores 104-107. Each core 104-107 executes instructions, accesses shared memory locations, and performs functions independently from the other cores 104-107).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
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/HUA J SONG/Primary Examiner, Art Unit 2133
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