Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 09/22/2026. Claims 1 – 14 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1, 4, 5 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. Pub. No. 2024/0291497.
Regarding claim 1. Fig. 3A of Lee et al. disclose an analog to digital converter (310; paragraph 0038) for converting an input signal (VINP, VINN) into a digital value (DOUT), the analog to digital converter (310) comprising a successive approximation register (314) a first and a second digital to analog converter (top and bottom DAC 316), a switch matrix (switching matrix Ψsar, Ψsar*), a comparator (313), and a comparator switch (comparator switch Ψ*int2) between a first and a second input of the comparator (+ and – inputs of 313), wherein the successive approximation register (314) is connected with its output (5b) to the first digital to analog converter (top DAC 316), to the second digital to analog converter (bottom DAC 316), wherein the switch matrix (switching matrix Ψ*sar) is configured for capacitively coupling (CINT1, CINT2, CINT12) the input signa (VINP, VINN) between the first input and the second input of the comparator (+ and – inputs of 313), or for capacitively coupling (CINT1, CINT2, CINT12) an output signal of the first digital to analog converter (output of top DAC 316) or an output signal of the second digital to analog converter (output of bottom DAC 316) or both (both top and bottom DAC 316) between the first input and the second input of the comparator (+ and – input of 313), and wherein an output of the comparator (output of 313) is connected to an input of the successive approximation register (input of SAR 314).
Regarding claim 4. The analog to digital converter according to claim 1, Fig. 3A further discloses wherein the analog to digital converter (310) comprises a controller (controller to generate switching control signals of 310) which is configured for controlling the switch matrix ((switching matrix Ψsar, Ψsar*).
Regarding claim 5. The analog to digital converter according to claim 4, Fig. 3A further discloses wherein the controller (controller to generate switching control signals of 310) is configured for controlling the comparator switch (comparator switch Ψ*int2) and the switch matrix (switching matrix Ψsar, Ψsar*) for capacitively coupling (CINT1, CINT2, CINT12) the input signal (VINP, VINN) between the first input and the second input of the comparator (+ and – inputs of 313) for sampling the input signal ((VINP, VINN) , and for controlling the comparator switch (comparator switch Ψ*int2) and the switch matrix (switching matrix Ψsar, Ψsar*) for capacitively coupling (CINT1, CINT2, CINT12) the output signal of the first digital to analog converter (output of top DAC 316) and the output signal of the second digital to analog converter (output of bottom DAC 316) between the first input and the second input of the comparator (+ and – input of 313) for conversion (conversion of 310).
Regarding claim 6. The analog to digital converter according to claim 4, Fig. 3A further discloses wherein the controller (controller to generate switching control signals of 310) is configured for controlling the comparator switch (comparator switch Ψ*int2) and the switch matrix (switching matrix Ψsar, Ψsar*) for capacitively (CINT1, CINT2, CINT12) coupling the output signal of the first digital to analog converter (output of top DAC 316) between the first input and the second input of the comparator (+ and – input of 313) or for capacitively (CINT1, CINT2, CINT12) coupling the output signal of the second digital to analog converter (output of bottom DAC 316) between the first input and the second input of the comparator (+ and – input of 313) for sampling (sampling of 313), and for controlling the comparator switch (comparator switch Ψ*int2) and the switch matrix (switching matrix Ψsar, Ψsar*) for capacitively (CINT1, CINT2, CINT12) coupling the output signal of the second digital to analog converter (output of bottom DAC 316) between the first input and the second input of the comparator (+ and – inputs of 313) for conversion (conversion of 313) after sampling the output of the first digital to analog converter (sampling output of top DAC 316), or for controlling the comparator switch (comparator switch Ψ*int2) and the switch matrix (switching matrix Ψsar, Ψsar*) for capacitively (CINT1, CINT2, CINT12) coupling the output signal of the first digital to analog converter (output of top DAC 316) between the first input and the second input of the comparator (+ and – inputs of 313) for conversion (conversion of 310) after sampling the output of the second digital to analog converter (sampling output of bottom DAC 316).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 2, 3, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. applied to claim 1 above in view of Aruga et al. Pub. No. 2010/0001892.
Regarding claim 2. Lee et al. applied to claim 1 above does not discloses wherein each of the digital to analog converters (top/bottom DAC 316) comprises a resistor string.
Fig. 4 of Aruga et al. disclose an SAR analog-to-digital converter comprising: a first and a second digital to analog converter (resistor string SUB-DAC and SDACPN1).
Lee et al. and Aruga et al. are common subject matter of DAC for SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate resistive DAC of Aruga et al. into DAC Lee et al. for the purpose of providing a resistive D/A converter that generates a voltage based on a digital signal by voltage division using a resistor string as suggested in paragraph 0004 of Argua et al.
Regarding claim 3. Lee et al. and Aruga et al. applied to claim 2 above, Fig. 4 of Aruga et al. further discloses wherein the first digital to analog converter (SUB-DAC) and the second digital to analog converter (SDACPN1) comprise identical resistor strings (String of 1R).
Regarding claim 10. Lee et al. and Aruga et al. applied to claim 2 above, Fig. 4 of Aruga et al. further discloses wherein each digital to analog converter (each of sub-DAC) comprises at least one multiplexer (SLNN, SLNB) controlled by an input digital code (DSUB) obtained from the output of the successive approximation register (CNTL3) for connecting an internal node of the resistor string (internal code for selection of Resistor string) to the output (VSUBN, VSUBP) of the digital to analog converter (SUB_DAC).
Allowable Subject Matter
7. Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the analog to digital converter is single ended, and wherein the analog to digital converter comprises a first capacitor and a second capacitor both connected with their second terminal to the first input of the comparator and wherein the switch matrix comprises a first switch between an input terminal for the input signal and a first terminal of the first capacitor, a second switch between the input terminal and a first terminal of the second capacitor, a third switch between the first digital to analog converter and the first terminal of the first capacitor, a fourth switch between the first digital to analog converter and the first terminal of the second capacitor, a fifth switch between the second digital to analog converter and the first terminal of the first capacitor, a sixth switch between the second digital to analog converter and the first terminal of the second capacitor.
8. Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the analog to digital converter is a differential analog to digital converter, and wherein the analog to digital converter comprises a first pair of capacitors connected with their second terminals respectively to the first and second input of the comparator and a second pair of capacitors connected with their second terminals respectively to the first and second input of the comparator and wherein the switch matrix comprises a first pair of switches between a pair of input terminals and first terminals of the first pair of capacitors, a second pair of switches between the pair of input terminals and first terminals of the second pair of capacitors, a third pair of switches between the first digital to analog converter and the first terminals of the first pair of capacitors, a fourth pair of switches between the first digital to analog converter and the first terminals of the second pair of capacitors, a fifth pair of switches between the second digital to analog converter and the first terminals of the first pair of capacitors, a sixth pair of switches between the second digital to analog converter and the first terminals of the second pair of capacitors.
9. Claim 12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the analog to digital converter is a differential analog to digital converter, wherein each digital to analog converter comprising a matrix of four switches and comprises a first multiplexer connected to an upper halve of the resistor string and a second multiplexer connected to a lower halve of the resistor string controlled by an input digital code obtained from the output of the successive approximation register using sign and magnitude coding wherein the magnitude controls the first and the second multiplexer and wherein the sign controls the matrix of four switches to connect the output of the first multiplexer to the positive output terminal of the digital to analog converter and the output of the second multiplexer to the negative output terminal of the digital to analog converter if the sign is positive, and the output of the first multiplexer to the negative output terminal of the digital to analog converter and the output of the second multiplexer to the positive output terminal of the digital to analog converter if the sign is negative.
10. Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: for a single ended analog to digital converter, wherein the resistor string of the first digital to analog converter and the resistor string of the second digital to analog converter are positioned such that a first symmetry axis and a second symmetry axis orthogonal to the first symmetry axis can be identified between the resistors and wherein any pair of resistors with a same index in the resistor string of the first digital to analog converter and the resistor string of the second digital to analog converter has their center of gravity right at the crossing of the first symmetry axis and the second symmetry axis.
Contact Information
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
02/18/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845