Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1-5, 10-16, 20, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YIM et al (Pub. No.: US 2017/0046210).
3. Regarding independent claim 1, YIM et al teaches an operating method of a nonvolatile memory device (Fig. 1, #100), the operating method comprising: applying a first verification voltage (Fig. 20, Vvfy1) to a plurality of selected memory cells (Fig. 3, paragraph [0020]) in a first program loop (Fig. 20, Vpgm1) that verifies pass or fail (Fig. 20, P/F checker (127)) of a first program state (Fig. 20, the state after Vpgm1) among a plurality of program states (Fig. 20, the state after Vpgm1-Vpgm7 for example); applying a second verification voltage (Fig. 20, Vvfy2) to the plurality of selected memory cells (Fig. 3, paragraph [0020]) in the first program loop (Fig. 20, Vpgm1) that verifies pass or fail (Fig. 20, P/F checker (127)) of a second program state (Fig. 20, the state of Vpgm2)among the plurality of program states (Fig. 20, the state after Vpgm1-Vpgm7 for example); applying a program voltage (Fig. 20, Vpgm2) to the plurality of selected memory cells (Fig. 3, paragraph [0020]) in a second program loop (Fig. 20, Vpgm2 loop); and based on the program voltage (Fig. 20, Vpgm2) being applied to the plurality of selected memory cells (Fig. 3, paragraph [0020]), verifying pass or fail (Fig. 20, P/F checker (127)) of the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2) for the plurality of selected memory cells (Fig. 3, paragraph [0020]) based on a result of applying the first verification voltage (Fig. 20, Vvfy1) and a result of applying the second verification voltage (Fig. 20, Vvfy2).
4. Regarding claim 2, 14, YIM et al teaches a method of applying the first verification voltage (Fig. 20, Vvfy1) is different (see Fig. 20, Vvfy1<Vvfy2) from a method of applying the second verification voltage (Fig. 20, Vvfy2).
5. Regarding claim 3, 15, YIM et al teaches when the plurality of selected memory cells (Fig. 3, paragraph [0020]) are a plurality of quadruple level cells (see Fig. 20), the plurality of program states (Fig. 20, the state after Vpgm1-Vpgm7 for example) include an erase state and program states (Fig. 20, where four level including erase state will have 15 states), and the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2) are adjacent to each other among the 15 program states (Fig. 20, where four level including erase state will have 15 states).
6. Regarding claim 4, 16, YIM et al teaches when the plurality of selected memory cells (Fig. 3, paragraph [0020]) are a plurality of triple level cells (Fig. 20, Vvfy1-Vvfy3), the plurality of program states (Fig. 20, the state after Vpgm1-Vpgm7 for example) include an erase state and seven program states (Fig. 20, where three level including seven states), and the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2)are adjacent to each other among the seven program states (Fig. 20, where three level including seven states).
7. Regarding claim 5, 17, YIM et al teaches verifying pass or fail (Fig. 20, P/F checker (127)) of the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2)includes: counting a number of first fail bits as the result of applying the first verification voltage (Fig. 20, Vvfy1) and counting a number of second fail bits (Fig. 5, CV_2, paragraph [0101], line 10) as the result of applying the second verification voltage (Fig. 20, Vvfy2); and determining whether the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2)pass based on a number of third fail bits (Fig. 5, paragraph [0101], lines 8-11, AV_3), the number of third fail bits (Fig. 5, paragraph [0101], lines 8-11, AV_3) being a sum of the number of first fail bits and the number of second fail bits (Fig. 5, CV_2).
8. Regarding claim 10, YIM et al teaches determining whether the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2)pass based on the number of third fail bits (Fig 5, AV_n paragraph [0101], line 8-12) includes: comparing (see Fig. 6, S130) the number of third fail bits and a number of third reference bits; and determining (Fig. 6, S130) that both the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2) pass (Fig. 6, No of S130) when the number of third fail bits is less than the number of third reference bits, wherein the number of third reference bits is a sum of a number of first reference bits (Fig. 5, RV_n) for the first program state (Fig. 20, the state after Vpgm1) and a number of second reference bits for the second program state (Fig. 20, Vpgm2).
9. Regarding claim 11, YIM et al teaches verifying pass or fail (Fig. 20, P/F checker (127)) of the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2) includes: counting a number of first fail bits (Fig. 5, CV_1, paragraph [0101], line 7) as the result of applying the first verification voltage (Fig. 20, Vvfy1) and counting a number of second fail bits (Fig. 5, CV_2, paragraph [0101], line 8) as the result of applying the second verification voltage (Fig. 20, Vvfy2); determining whether the first program state (Fig. 20, the state after Vpgm1) passes based on the number of first fail bits (Fig. 20, P/F Checker (127)); and determining whether the second program state (Fig. 20, the state of Vpgm2) passes based on the number of second fail bits (Fig. 20, P/F Checker (127)).
10. Regarding claim 12, YIM et al teaches verifying pass or fail (Fig. 20, P/F checker (127)) of the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2) includes: counting (Fig. 5, #127a), by a first mass bit counter (Fig. 5, #127a) connected to a first page buffer block (Fig. 5, PB_1 for example), a number of first fail bits (see Fig. 20) according to the result of applying the first verification voltage (Fig. 20, Vvfy1) ; comparing (see Fig. 5, #127b) the number of first fail bits (Fig. 5, CV_1) and a number of first reference bits (Fig. 5, RV_n) for the first program state (Fig. 20, the state after Vpgm1); determining, by the first mass bit counter (Fig. 5, #127), that the first program state (Fig. 20, the state after Vpgm1) passes when the number of first fail bits (see Fig. 20) is less than the number of first reference bits (Fig. 5, RV_n); counting, by a second mass bit counter (Fig. 5, #127a) connected to a second page buffer block (Fig. 5, PB_2), a number of second fail bits (Fig. 5, CV_2) according to the result of applying the second verification voltage (Fig. 20, Vvfy2); comparing the number of second fail bits (Fig. 5, CV_2) and a number of second reference bits (Fig. 5, RV_n) for the program state (Fig. 20, the state after Vpgm2); and determining, by the second mass bit counter (Fig. 5, #127a), that the second program state (Fig. 20, the state of Vpgm2)passes when the number of second fail bits (Fig. 5, CV_n) is less than the number of second reference bits (Fig. 5, RV_n).
11. Regarding independent claim 13, YIM et al teaches a nonvolatile memory device (Fig. 1, #100) comprising: a memory cell array (Fig. 3) including a plurality of memory cells (Fig. 3, #121); a page buffer circuit (Fig. 5, #125) including a plurality of page buffer blocks (Fig. 5, #125, PB_1 for example), the plurality of page buffer blocks (Fig. 5, #125, PB_1 for example) connected to the memory cell array (Fig. 3) through a plurality of bit lines; a control logic configured to apply a first verification voltage (Fig. 20, Vvfy1) to a plurality of selected memory cells (Fig. 3, paragraph [0020]) among the plurality of memory cells in a first program loop (Fig. 20, Vpgm1) that verifies pass or fail (Fig. 20, P/F checker (127)) of a first program state (Fig. 20, the state after Vpgm1) among a plurality of program states (Fig. 20, the state after Vpgm1-Vpgm7 for example), apply a second verification voltage (Fig. 20, Vvfy2) to the plurality of selected memory cells (Fig. 3, paragraph [0020]) in the first program loop (Fig. 20, Vpgm1) that verifies pass or fail (Fig. 20, P/F checker (127)) of a second program state (Fig. 20, the state of Vpgm2) among the plurality of program state, and apply a program voltage to the plurality of selected memory cells (Fig. 3, paragraph [0020]) in a second program loop (Fig. 20, Vpgm2 loop); and a mass bit counter configured to verify, based on the program voltage being applied to the plurality of selected memory cells (Fig. 3, paragraph [0020]), pass or fail (Fig. 20, P/F checker (127)) of the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2)for the plurality of selected memory cells (Fig. 3, paragraph [0020]) based on a result of applying the first verification voltage (Fig. 20, Vvfy1) and a result of applying the second verification voltage (Fig. 20, Vvfy2).
12. Regarding independent claim 20, YIM et al teaches an operating method of a nonvolatile memory device (Fig. 1, #100), the operating method comprising: applying a program voltage (Fig. 20, Vpgm1 for example) to a plurality of selected memory cells (Fig. 3, paragraph [0020]); applying a first verification voltage (Fig. 20, Vvfy1) to the plurality of selected memory cells (Fig. 3, paragraph [0020]) that verifies pass or fail (Fig. 20, P/F checker (127)) of a first program state (Fig. 20, the state after Vpgm1) among a plurality of program states (Fig. 20, the state after Vpgm1-Vpgm7 for example); applying a second verification voltage (Fig. 20, Vvfy2) to the plurality of selected memory cells (Fig. 3, paragraph [0020]) that verifies pass or fail (Fig. 20, P/F checker (127)) of a second program state (Fig. 20, the state of Vpgm2)among the plurality of program states (Fig. 20, the state after Vpgm1-Vpgm7 for example); and after applying the first verification voltage (Fig. 20, Vvfy1) and the second verification voltage (Fig. 20, Vvfy2) to the plurality of selected memory cells (Fig. 3, paragraph [0020]), verifying pass or fail (Fig. 20, P/F checker (127)) of the first program state (Fig. 20, the state after Vpgm1) and the second program state (Fig. 20, the state of Vpgm2) for the plurality of selected memory cells (Fig. 3, paragraph [0020]) based on a result (Fig. 20) of applying the first verification voltage (Fig. 20, Vvfy1) and a result (see Fig. 20) of applying the second verification voltage (Fig. 20, Vvfy2).
Allowable Subject Matter
13. Claim(s) 6-9, 17-19 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
14. With respect to claims 6, 17, there is no teaching, suggestion, or motivation for combination in the prior art to determining whether the first program state the second program state pass based on the number of third fail bits includes: comparing the number of third fail bits and a number of fourth reference bits; and when the number of third fail bits is less than the number of fourth reference bits, determining that both the first program state and the second program state pass, wherein the number of fourth reference bits is a value less than a number of third reference bits, the number of third reference bits being a sum of a number of first reference bits for the first program state and a number of second reference bits for the second program state.
15. With respect to dependent claims 7, 18, since these claims are depending on claims 6, 17, therefore claims 7, 18 are allowable subject matter.
16. With respect to independent claim 8, there is no teaching, suggestion, or motivation for combination in the prior art to determining whether the first program state and the second program state pass based on the number of third fail bits includes: comparing the number of third fail bits and a number of fifth reference bits; and when the number of third fail bits is less than the number of fifth reference bits, determining that both the first program state and the second program state pass, wherein the number of fifth reference bits is a value greater than a number of third reference bits, the number of third reference bits being a sum of a number of first reference bits for the first program state and a number of second reference bits for the second program state.
17. With respect to dependent claim 9, since these claims are depending on claim 8, therefore claim 9 are allowable subject matter.
18. With respect to claim 19, there is no teaching, suggestion, or motivation for combination in the prior art to wherein the mass bit counter includes a first mass bit counter and a second mass bit counter, the plurality of page buffer blocks include a first page buffer block and a second page buffer block, the first mass bit counter is connected to the first page buffer block and is configured to count a number of first fail bits according to the result of applying the first verification voltage, compare the number of first fail bits and a number of first reference bits for the first program state, and determine that the first program state passes when the number of first fail bits is less than the number of first reference bits, and the second mass bit counter is connected to the second page buffer block and is configured to count a number of second fail bits according to the result of applying the second verification voltage, compare the number of second fail bits and a number of second reference bits for the second program state, and determine that the second program state passes when the number of second fail bits is less than the number of second reference bits.;
Conclusion
19. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Song et al (Pub. No: US 2012/0314500).
Song et al (Pub. No: US 2012/0314500) shows multi-level verify voltages.
20. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
05/13/2026
/HAN YANG/
Primary Examiner, Art Unit 2824
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