DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the application filed September 27, 2024.
Claims 1-19 are pending and are presenting for examination.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
5. The specification is objected to for information provided on page 1, paragraph 1, where the current status of the Cross Reference to Related Applications should be updated. See MPEP 608.01[R-5] and 37 CFR 1.78.
Claim Objections
6. Claims 1-19 are objected to because of the following informalities:
As to claims 1-19, they appear to be repeating the same number (i.e. claim 1 twice) and should be re-numbered as 1-20 instead.
As to claim 1 (presumably claim 2) recites to include the following limitation “wherein the storage of the second tables to the memory” seems lacking antecedent basis for this limitation in the claim.
As to claim 8 (presumably claim 9) recites to include the following limitation “wherein the storing of the second tables to the memory” seems lacking antecedent basis for this limitation in the claim.
Appropriate correction is required.
Double Patenting
7. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
8. Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,159,133 B2.
The claims of the current application and the claims of the reference patent are compared in the table below.
Current Application
U.S. Patent No. 12,159,133 B2
1. An information handling system comprising: a memory to store a current basic input/
output system (BIOS) firmware image; and a processor to communicate with the memory, the processor to:
during a BIOS update boot mode of the information handling system:
create a first plurality of tables associated with a BIOS firmware update image;
compare the first plurality of table to a second plurality of tables, wherein the second plurality of tables are associated with the current BIOS firmware image; and
in response to a difference being determined between the first and second tables, abort the BIOS update boot mode and generate an error log.
1. The information handling system of claim 1, wherein the storage of the second tables to the memory includes the processor to create a hand-off block, and execute the hand-off block to store the second tables in the memory.
2. The information handling system of claim 1, wherein the processor further to provide the error log to a manufacturer as telemetry data.
3. The information handling system of claim 3, wherein the processor further to receive a corrected BIOS firmware update image.
4. The information handling system of claim 4, wherein the corrected BIOS firmware update image is based on the telemetry data.
5.The information handling system of claim 1, wherein the aborted BIOS update boot mode prevents a BIOS update failure resulting from the difference.
6. The information handling system of claim 1, wherein the second tables includes a structure variable table for the current BIOS firmware image, a common configuration patch map table, and a platform configuration patch map table.
7. A method comprising: storing, in a memory of an information handling system, a current basic input/output system (BIOS) firmware image; during a BIOS update boot mode of the information handling system:
creating
a first plurality of tables associated with a BIOS firmware update image;
comparing the first plurality of table to a second plurality of tables, wherein the second plurality of tables are associated with the current BIOS firmware image; and
in response to a difference being determined between the first and second tables, aborting, by the processor, the BIOS update boot mode and generate an error log.
8. The method of claim 8, wherein the storing of the second tables to the memory includes, the method further comprises: creating a hand-off block; and executing the hand-off block to store the second tables in the memory.
9. The method of claim 9, further comprising providing the error log to a manufacturer as telemetry data.
10. The method of claim 10, further comprising receiving a corrected BIOS firmware update image.
11. The method of claim 11, wherein the corrected BIOS firmware update image is based on the telemetry data.
12. The method of claim 9, wherein based on the aborting of the BIOS update boot mode, the method further comprises preventing a BIOS update failure resulting from the difference.
13. The method of claim 9, wherein the second tables includes a structure variable table for the current BIOS firmware image, a common configuration patch map table, and a platform configuration patch map table.
14. An information handling system comprising: a memory to store a current basic input/output system (BIOS) firmware image; and a processor to:
load an initial boot block from the current BIOS firmware image;
extract a first mapping table from the BIOS firmware update image;
compare the first mapping table to a second mapping table, wherein the second mapping table is created from the current BIOS firmware image stored in the memory; and
in response to a difference between the first and second mapping tables, abort a BIOS firmware image update and create an error log.
15. The information handling system of claim 15, wherein the processor further to provide the error log to a manufacturer as telemetry data.
16. The information handling system of claim 15, wherein the difference is based on the BIOS firmware update image including a first BIOS reference code different from a
second BIOS reference code in the current BIOS firmware image.
17. The information handling system of claim 17, wherein the processor further to receive a corrected BIOS firmware update image based on the telemetry data.
18. The information handling system of claim 15, wherein the difference is based on the BIOS firmware update image including a first BIOS reference code that is different from a second BIOS reference code in the current BIOS firmware image.
19. The information handling system of claim 15, wherein the difference is based on the BIOS firmware update image including a first BIOS setup that is different from a second BIOS setup in the current BIOS firmware image.
1. An information handling system comprising: a memory to store a current basic input/
output system (BIOS) firmware image; and a processor to communicate with the memory, the processor to:
during a regular boot mode of the information handling:
create a first plurality of tables associated with the current BIOS firmware image;
store the first tables to the memory; and receive a BIOS firmware update image; and during a BIOS update boot mode of the information handling system: create a second plurality of tables associated with the BIOS firmware update image;
compare the first and second tables; and
in response to a difference being determined between the first and second tables, abort the BIOS update boot mode and generate an error log.
2. The information handling system of claim 1, wherein the storage of the first tables to the memory includes the processor to create a hand-off block, and execute the hand-off block to store the first tables in the memory.
3. The information handling system of claim 1, wherein the processor further to provide the error log to a manufacturer as telemetry data.
4.The information handling system of claim 3, wherein the processor further to receive a corrected BIOS firmware update image.
5. The information handling system of claim 4, wherein the corrected BIOS firmware update image is based on the telemetry data.
6. The information handling system of claim 1, wherein the aborted BIOS update boot mode prevents a BIOS update failure resulting from the difference.
7. The information handling system of claim 1, wherein the first tables includes a structure variable table for the current BIOS firmware image, a common configuration patch map table, and a platform configuration patch map table.
8. A method comprising: storing, in a memory of an information handling system, a current basic input/output system (BIOS) firmware image; during a regular boot mode of the information handling:
creating, by a processor of the information handling system, a first plurality of tables associated with the current BIOS firmware image;
storing the first tables to the memory; and receiving a BIOS firmware update image; and
during a BIOS update boot mode of the information handling system: creating a second plurality of tables associated with the BIOS firmware update image;
comparing the first and second tables; and
in response to a difference being determined between the first and second tables, aborting, by the processor, the BIOS update boot mode and generate an error log.
9. The method of claim 8, wherein the storing of the first tables to the memory includes, the method further comprises: creating a
hand-off block; and executing the hand-off block to store the first tables in the memory.
10. The method of claim 9, further comprising providing the error log to a manufacturer as telemetry data.
11. The method of claim 10, further comprising receiving a corrected BIOS firmware update image.
12. The method of claim 11, wherein the corrected BIOS firmware update image is based on the telemetry data.
13. The method of claim 9, wherein based on the aborting of the BIOS update boot mode, the method further comprises preventing a BIOS update failure resulting from the difference.
14. The method of claim 9, wherein the first tables includes a structure variable table for the current BIOS firmware image, a common configuration patch map table, and a platform configuration patch map table.
15. An information handling system comprising: a memory to store a current basic input/output system (BIOS) firmware image; and a processor to:
load an initial boot block from the current BIOS firmware image;
load an original equipment manufacturer boot block from a BIOS firmware update image;
extract a first mapping table from the BIOS firmware update image;
compare the first mapping table to a second mapping table, wherein the second mapping table is created from the current BIOS firmware image stored in the memory; and
in response to a difference between the first and second mapping tables, abort a BIOS firmware image update and create an error log.
16. The information handling system of claim 15, wherein the processor further to provide the error log to a manufacturer as telemetry data.
18. The information handling system of claim 15, wherein the difference is based on the BIOS firmware update image including a first BIOS reference code that is different from a second BIOS reference code in the current BIOS firmware image.
17. The information handling system of claim 16, wherein the processor further to receive a corrected BIOS firmware update image based on the telemetry data
19. The information handling system of claim 15, wherein the difference is based on the BIOS firmware update image including a first BIOS setup that is different from a second BIOS setup in the current BIOS firmware image.
19. The information handling system of claim 15, wherein the difference is based on the BIOS firmware update image including a first BIOS setup that is different from a second BIOS setup in the current BIOS firmware image.
Based on the comparison of the above table, indicates that, although claims 1-19 of U.S. Patent Application No. ‘133 are not identical, they are not patentably distinct from claims 1-19 of the current examined application because both claimed inventions are directed toward safely handle BIOS updates via detect configuration mismatches before completing the flash. If a difference is found, the update is aborted and an error log is generated, in which the claims of U.S. Patent Application No. ‘133 are read on to claims 1-19 of the current examined application.
Thus, claims 1-19 of the current examined application are unpatentable over 1-19 of the U.S. Patent Application No. ‘133 and as such are unpatentable for anticipated-type double patenting.
Allowable Subject Matter
9. The prior arts of record or made of record, taken alone or in combination do not disclose and/or suggest, and/or motivation to combine, “create a first plurality of tables associated with a BIOS firmware update image; compare the first plurality of table to a second plurality of tables, wherein the second plurality of tables are associated with the current BIOS firmware image; and in response to a difference being determined between the first and second tables, abort the BIOS update boot mode and generate an error log” as limitations recited in as such manners as in independent claim 1.
The prior arts of record or made of record, taken alone or in combination do not also disclose and/or suggest, and/or motivation to combine, “ extract a first mapping table from the BIOS firmware update image; compare the first mapping table to a second mapping table, wherein the second mapping table is created from the current BIOS firmware image stored in the memory; and in response to a difference between the first and second mapping tables, abort a BIOS firmware image update and create an error log” as limitations recited in as such manners as in independent claim 14.
Conclusion
10. The prior art made of record and not relied upon (cited on 892 form) is considered pertinent to application disclosure.
Liu et al. (US-8239665-B2) disclosed configuring boot options of an information handling system (IHS) and boot tables comparison.
Vidyadhara et al. (US-11726880-B1) disclosed fault tolerance and debug analysis during a boot process and hand-off block creation.
Butcher et al. (US-9507581-B2) disclosed firmware updates using table identifier for comparison.
Samuel et al. (US-10776488-B2) disclosed halting boot process if determining that table of approved firmware does not match.
Cheng et al. (US-20240311138-A1) disclosed a BIOS update subsystem that is coupled to a memory system and a BIOS.
Li et al. (US-11068596-B2) disclosed reporting the status of a persistent memory firmware update.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARINA LEE whose telephone number is (571)270-1648. The examiner can normally be reached Monday to Friday (8 am to 4: 30 pm ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung S. Sough can be reached on (571)-272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARINA LEE/Primary Examiner, Art Unit 2192
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