DETAILED ACTION
This office action is responsive to preliminary amendment filed on September 27, 2024 in this application Lee, U.S. Patent Application No. 18/899,623, (Filed September 27, 2024) claiming priority to KR10-2024-0019202 (2/7/2024). Claims 1 – 20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on March 11, 2025 and September 27, 2024 are in compliance with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609. The references listed therein have been considered and placed in the application file.
Claim Rejections 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 – 14 and 16 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Izumi et al., United States Patent Application Publication No. 2019/0129710 (Published May 2, 2019, filed May 22, 2017) (“Izumi”) in view of Kan et al., United States Patent Application Publication No. 2018/0081569 (Published March 22, 2018, filed September 22, 2016) (“Kan”).
Claims 1, 10, and 16
With respect to claims 1, 10, and 16 Izumi teaches the invention as claimed including an automotive device comprising:
an electronic control unit (ECU) configured to send a code request; a shared storage device including a nonvolatile memory device… the nonvolatile memory device configured to store a plurality of code segments that form an entire code corresponding to the code request,… and a system memory device configured to receive the at least one code segment… and store the at least one code segment, and to output the at least one code segment to the ECU that has sent the code request, wherein the ECU receives the at least one code segment from the system memory device and overlays the at least one code segment onto an executable code set and executes a function based on the executable code set. {A vehicle requests and receives a plurality of ECU updates from a server where vehicle Gateway 10 acts as a shared memory and controller to receive the updates, store the updates in its nonvolatile storage unit 13, then when an update is to be transferred to a target ECU for installation the update is moved from the nonvolatile storage unit 13 of the Gateway 10 to RAM 12 which acts as a buffer to hold update data prior to the Gateway 10 CPU 11 transferring the update to target ECU 30 which receives the update via its RAM 32 which acts as another buffer prior to CPU 31 of the target ECU 30 overwriting the old program in its storage area 33 with the received update. Izumi at ¶¶ 0095 & 0103 (update download request and transfer to vehicle Gateway 10); id. at fig. 2 and ¶¶ 0059, 0060, & 0104 (Gateway 10 stores updates in its nonvolatile storage unit 13); id. at figs. 3 & 5 and ¶¶ 0116 – 0118 (Gateway 10 transfers update to ECU 30); id. at ¶¶ 0078 & 0118 (overwriting ECU 30 program in storage unit 33 with update); id. at ¶¶ 0056, 0058, 0069, 0070 (RAM is used as buffer by CPU in both Gateway 10 and ECU 30 CPUs); id. at fig. 5 (update program flows from server to Gateway 10 storage to ECU 30 storage).}
However, Izumi doesn’t explicitly teach the limitation:
and a storage controller/segment table, …and the storage controller configured to load at least one code segment of the plurality of code segments from the nonvolatile memory device into a buffer memory based on characteristic information of each of the plurality of code segments; … from the buffer memory… {Kan does teach this limitation. Kan teaches that transferring data from storage to memory and back, as taught in Izumi, may include a memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address, size, the frequency of access, as well as the hit rate in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be maintained in caches rather than in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0035, 0040 – 0045, 0048, 0049; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers).
Izumi and Kan are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of memory management, and both are trying to solve the problem of how to transfer data between different memory structures.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine transferring data from storage to memory and back, as taught in Izumi using a storage controller, buffer, and segment tables, as taught in Kan. Kan teaches that using segment characterization information can improve cache memory usage, hit rates, and access times. Id. at ¶¶ 0017 & 0037. Therefore, one having ordinary skill in the art would have been motivated to combine transferring data from storage to memory and back, as taught in Izumi using a storage controller, buffer, and segment tables, as taught in Kan, for the purpose of using a known memory management optimization method with an ECU memory management method that requires reading and writing data into various memories to increase the speed and efficiency of the various read/write events.}
Claims 2, 13, and 17
With respect to claims 2, 13, and 17 Izumi and Kan teaches the invention as claimed including:
wherein the shared storage device includes a segment table that includes the characteristic information, and wherein the characteristic information includes for each of the plurality of code segments,/segment identifier (ID) indicating requester information for the ECU/, requester information for the ECU, a logical address, a current physical address, size information, access frequency information, / and least recently used (LRU) information or the code segment / a hit ratio. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address, size, the frequency of access, as well as the hit rate in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be maintained in caches rather than in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0035, 0040 – 0045, 0048, 0049; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers).}
Claims 3 and 19
With respect to claims 3 and 19 Izumi and Kan teaches the invention as claimed including:
wherein the characteristic information further includes a previous physical address of each of the plurality of code segments along with the current physical address / and an erase count. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be maintained in caches rather than in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
Claim 4
With respect to claim 4 Izumi and Kan teaches the invention as claimed including:
wherein the storage controller reads the at least one code segment based on the previous physical address in the nonvolatile memory device when a code segment corresponding to a requested logical address corresponding to the code request is unable to be read from the current physical address in the nonvolatile memory device. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be maintained in caches rather than in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
Claim 5
With respect to claim 5 Izumi and Kan teaches the invention as claimed including:
wherein the segment table selectively deletes the characteristic information of the at least one code segment based on the hit ratio of each of the plurality of code segments. {Segments with low hits may be removed from cache. Kan at ¶ 0064.}
Claim 6
With respect to claim 6 Izumi and Kan teaches the invention as claimed including:
wherein the storage controller comprises: a segment analyzer that is configured to determine a code region based on a locality, a read access frequency, and an update status of the nonvolatile memory device and to extract the characteristic information of each of the plurality of code segments stored in the code region, a segment table, which stores the characteristic information for each of the plurality of code segments that has been extracted, a segment controller that is configured to read the at least one code segment corresponding to the code request from the code region of the nonvolatile memory device based on the characteristic information and output the at least one code segment, and the buffer memory configured to store the at least one code segment that has been read and output the at least one code segment to the system memory device. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be maintained in caches rather than in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
Claim 7
With respect to claim 7 Izumi and Kan teaches the invention as claimed including:
wherein the segment analyzer is configured to store or migrate the plurality of code segments to one of the buffer memory, a single-level cell (SLC) region, a multi-level cell (MLC) region, or a default region within the nonvolatile memory device based on the read access frequency of each of the plurality of code segments. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be added to or removed from caches rather than remain in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049, 0064; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
Claim 8
With respect to claim 8 Izumi and Kan teaches the invention as claimed including:
further comprising a translation agent (TA), wherein when there is no physical address of the at least one code segment requested by the code request, the shared storage device receives a newly assigned physical address for a logical address included in the code request from the TA, and transmits the at least one code segment to the newly assigned physical address in the system memory device. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be added to or removed from caches rather than remain in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049, 0064; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
Claim 9
With respect to claim 9 Izumi and Kan teaches the invention as claimed including:
wherein the shared storage device maps the newly assigned physical address with the logical address and updates the characteristic information of the at least one code segment corresponding to the code request. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be added to or removed from caches rather than remain in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049, 0064; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
Claim 11
With respect to claim 11 Izumi and Kan teaches the invention as claimed including:
wherein the host is configured to: execute a function based on an executable code set that includes a main code, an overlay area, and code data, update the executable code set by overlaying the at least one code segment received from the system memory device onto the overlay area, and execute the function based on the executable code set that has been updated. {A vehicle requests and receives a plurality of ECU updates from a server where vehicle Gateway 10 acts as a shared memory and controller to receive the updates, store the updates in its nonvolatile storage unit 13, then when an update is to be transferred to a target ECU for installation the update is moved from the nonvolatile storage unit 13 of the Gateway 10 to RAM 12 which acts as a buffer to hold update data prior to the Gateway 10 CPU 11 transferring the update to target ECU 30 which receives the update via its RAM 32 which acts as another buffer prior to CPU 31 of the target ECU 30 overwriting the old program in its storage area 33 with the received update. Izumi at ¶¶ 0095 & 0103 (update download request and transfer to vehicle Gateway 10); id. at fig. 2 and ¶¶ 0059, 0060, & 0104 (Gateway 10 stores updates in its nonvolatile storage unit 13); id. at figs. 3 & 5 and ¶¶ 0116 – 0118 (Gateway 10 transfers update to ECU 30); id. at ¶¶ 0078 & 0118 (overwriting ECU 30 program in storage unit 33 with update); id. at ¶¶ 0056, 0058, 0069, 0070 (RAM is used as buffer by CPU in both Gateway 10 and ECU 30 CPUs); id. at fig. 5 (update program flows from server to Gateway 10 storage to ECU 30 storage).}
Claim 12
With respect to claim 12 Izumi and Kan teaches the invention as claimed including:
wherein the storage controller extracts a code region from the nonvolatile memory device based on a locality, an access frequency, and an update status of a region in which the plurality of code segments are stored, and stores address information of the code region in the segment table. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be added to or removed from caches rather than remain in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049, 0064; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
Claim 14
With respect to claim 14 Izumi and Kan teaches the invention as claimed including:
wherein: the storage controller further includes an address translation cache that stores mapping information between logical addresses and physical addresses, when there is no mapping information for a physical address corresponding to a logical address included in the code request, the storage controller sends an address translation request to a translation agent (TA), and in response to receipt of an address translation service response for a newly assigned physical address that has been newly assigned by the TA, the storage controller transmits the at least one code segment that has been read to the newly assigned physical address in the system memory device. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be added to or removed from caches rather than remain in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049, 0064; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
Claim 18
With respect to claim 18 Izumi and Kan teaches the invention as claimed including:
wherein the storage controller sequentially reads the plurality of code segments …based on the characteristic information, stores the plurality of code segments that have been sequentially read in a buffer memory, {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be added to or removed from caches rather than remain in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049, 0064; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
associated with the function executed by the ECU from the nonvolatile memory device … and transmits the plurality of code segments to the system memory device. {A vehicle requests and receives a plurality of ECU updates from a server where vehicle Gateway 10 acts as a shared memory and controller to receive the updates, store the updates in its nonvolatile storage unit 13, then when an update is to be transferred to a target ECU for installation the update is moved from the nonvolatile storage unit 13 of the Gateway 10 to RAM 12 which acts as a buffer to hold update data prior to the Gateway 10 CPU 11 transferring the update to target ECU 30 which receives the update via its RAM 32 which acts as another buffer prior to CPU 31 of the target ECU 30 overwriting the old program in its storage area 33 with the received update. Izumi at ¶¶ 0095 & 0103 (update download request and transfer to vehicle Gateway 10); id. at fig. 2 and ¶¶ 0059, 0060, & 0104 (Gateway 10 stores updates in its nonvolatile storage unit 13); id. at figs. 3 & 5 and ¶¶ 0116 – 0118 (Gateway 10 transfers update to ECU 30); id. at ¶¶ 0078 & 0118 (overwriting ECU 30 program in storage unit 33 with update); id. at ¶¶ 0056, 0058, 0069, 0070 (RAM is used as buffer by CPU in both Gateway 10 and ECU 30 CPUs); id. at fig. 5 (update program flows from server to Gateway 10 storage to ECU 30 storage).}
Claim 20
With respect to claim 20 Izumi and Kan teaches the invention as claimed including:
wherein a segment analyzer is configured to store or migrate the plurality of code segments to one of a buffer memory, a single- level cell (SLC) region, a multi-level cell (MLC) region, or a default region within the nonvolatile memory device based on the access frequency of each of the plurality of code segments. {A memory controller that uses a buffer to store data in and read data from non-volatile memory locations where the data is transferred in the form of data segments that are identified by “logical block address” and may be tracked via characteristic information stored in table form, including flash translation layer tables and segment use database, where the characteristic data includes logical address, physical address (including previous physical addresses in FTL table ¶ 0043), size, the frequency of access, hit rate and I/O operations such as erases in order to perform logical-physical address look up for data requests and to determine which data segments and table information should be added to or removed from caches rather than remain in the storage. Kan at Abstract; id. at ¶¶ 00015, 0017, 0034, 0035, 0040 – 0045, 0048, 0049, 0064; id. at ¶¶ 0031, 0047, & fig. 2 (memory controller accesses non-volatile memory 212/214/218/220 and uses RAM buffer for transfers); id. at ¶¶ 0017, 0026, 0032, 0044 (tracking erase operations).}
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Izumi in view of Kan and Prakash et al. United States Patent Application Publication No. 2024/0354257 (Published October 24, 2024, filed April 18, 2023) (“Prakash”).
Claim 15
With respect to claim 15 Izumi and Kan teaches the invention as claimed, however, Izumi and Kan doesn’t explicitly teach the limitation::
wherein when there is no mapping information for a physical address corresponding to a logical address included in the code request, the storage controller transmits the at least one code segment that has been read to an input/output memory management unit (IOMMU), and the IOMMU transmits the at least one code segment to a newly assigned physical address in the system memory device that corresponds to the logical address. {Prakash does teach this limitation. Prakash teaches that transferring data from storage to memory and back, as taught in Izumi and Kan, may include using an IOMMU to assign a new physical address for a virtual [logical] address request. Prakash at Abstract; id. at ¶¶ 0029 & 0035.
Izumi, Kan, and Prakash are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of memory management, and both are trying to solve the problem of how to transfer data between different memory structures.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine transferring data from storage to memory and back, as taught in Izumi and Kan using IOMMU to assign new physical addresses in response to a virtual address request, as taught in Izumi and Prakash. Prakash teaches an IOMMU can perform new address allocation. Id. at ¶ 0029. Therefore, one having ordinary skill in the art would have been motivated to combine transferring data from storage to memory and back, as taught in Izumi and Kan using IOMMU to assign new physical addresses in response to a virtual address request, as taught in Izumi and Prakash, for the purpose of using a known module to assign new physical address with a method that can require requesting a new address.}
Conclusion
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//T.H./ September 17, 2026
Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199
