Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/03/2025, 04/24/2025 and 09/27/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3.) Claim(s) 1-4 and 8-11 is/are rejected under 35 U.S.C. 102 (a1) (a2) as being anticipated by Liao et al. (US Pub No.: 2023/0215771A1).
With regard to Claim 1, Liao et al. disclose an image sensing device (Electronic device 10, Figure 1; Paragraph 0026; Abstract), comprising:
a pixel array including pixel units (SU) (The electronic device 10 may include a plurality of sensing units SU, Paragraphs 0028, 0039 and Figures 1-2) configured to generate photocharge in response to incident light (The sensing units SU may be optical sensors for example, and each of the sensing units SU may include a sensing element P1, a thin film transistor T1, a thin film transistor T2 and a thin film transistor T3, but not limited thereto. The sensing element P1 may include a photodiode, a PIN diode or other suitable photoelectric conversion elements, but not limited thereto, Paragraph 0031; Figures 1-2), the pixel units including a plurality of first pixel transistors located in different rows of the pixel array (See transistors T1, T2 and T3 located in different rows, Paragraphs 0031-0033; Figure 2);
a plurality of first upper signal lines respectively connected to the plurality of first pixel transistors (See signal lines 102 and 106, Paragraphs 0034-0035; Figure 2);
a first test line, separated from and commonly connected to, the plurality of first upper signal lines (First test line 1101 is connected to a plurality of first upper signal lines 102 and 106, Figure 3; Paragraphs 0040-0045, 0047, 0055);
a first test pad (118) connected to the first test line (118 is connected to 1101) and configured to provide a first test signal to the first test line (The electronic device 10 may include a plurality of pads 116 (or may be referred to as the first pads) and a plurality of test pads 118 disposed on the substrate 100. The thin film transistors TR in different transistor rows can be turned on by transmitting switch signals through different signal lines 124, and the test signals can be transmitted to the corresponding sensing units SU through the pads 116, thus the function of the sensing units SU can be checked through the test pads 118. More specifically, the pads 116 may be electrically connected to a driving unit 126, the driving unit 126 may provide test signals to the corresponding sensing units SU, and the test pads 118 may receive the test signals to determine whether the function of the sensing units SU is normal, Paragraphs 0040, 0047, 0054-0055; Figures 1-3); and
a first test transistor connected to the first test line and the first test pad and configured to enable or disable a test operation by selectively providing the first test signal to the first test line (See transistor TR1. The thin film transistors TR in different transistor rows can be turned on by transmitting switch signals through different signal lines 124, and the test signals can be transmitted to the corresponding sensing units SU through the pads 116, thus the function of the sensing units SU can be checked through the test pads 118, Paragraphs 0044-0047, 0054; Figure 3) wherein
during the test operation, the first test signal is provided to the plurality of first pixel transistors located in different rows of the pixel array through the first test transistor, the first test line, and the plurality of first upper signal lines (The signal line 1101 (such as the signal line that can output the sensing signal) may be electrically connected to the pad 1161, and the pad 1161 may be electrically connected to one of the thin film transistors TR in the transistor row TR1. The signal line 1102 may be electrically connected to the pad 1162, and the pad 1162 may be electrically connected to one of the thin film transistors TS in the transistor row TR2. The signal line 1103 may be electrically connected to the pad 1163, and the pad 1163 may be electrically connected to another one of the thin film transistors TR in the transistor row TR1, Paragraphs 0044-0047, 0054-0055; Figures 1-3).
Regarding Claim 2, Liao et al. disclose the image sensing device according to claim 1, wherein: each of the plurality of first pixel transistors is a reset transistor, a selection transistor, a transfer transistor, or a gain conversion transistor (See transistors T2 and T3. A gate of the thin film transistor T2 may be electrically connected to the signal line 106. For example, the signal line 106 may provide a reset signal to the thin film transistor T2. A gate of the thin film transistor T3 may be electrically connected to the signal line 102, a first end of the thin film transistor T3 may be electrically connected to the second end of the thin film transistor T1, and a second end of the thin film transistor T3 may be electrically connected to the signal line 110. The thin film transistor T3 may be used as a reading transistor, and the thin film transistor T3 or the sensing unit SU can be controlled to output a sensing signal to the signal line 110 by the switch signal of the signal line 102, Paragraphs 0034-0035; Figures 1-3).
In regard to Claim 3, Liao et al. disclose the image sensing device according to claim 1, further comprising: a plurality of first lower signal lines(Signal lines 124, Paragraph 0043; Figure 3) respectively connected to the plurality of first upper signal lines (102 and 106 connected to 124, Figure 3), wherein the plurality of first pixel transistors, the plurality of first upper signal lines, and the first test line are disposed in a first substrate included in the pixel array (The transistors, upper signal lines 102, 106 along with the first test line 110 (1101) are included in the sensing region AR, Paragraphs 0026, 0040-0048; Figures 1-3); and the plurality of first lower signal lines (124) is disposed in a second substrate located below the first substrate (The non-sensing region PR of the substrate 100 may include a multiplexer region 120, and the multiplexer region 120 may be disposed between the pad region 112 and the pad region 114 in the direction Y, but not limited thereto. The electronic device 10 may include a plurality of multiplexers 12. One of the multiplexers 122 may include a plurality of thin film transistors TR and a plurality of signal lines 124, Paragraphs 0040-0047; Figures 1-3).
With regard to Claim 4, Liao et al. disclose the image sensing device according to claim 1, wherein the pixel array further includes: a plurality of second pixel transistors disposed in different rows from one another (See transistors connected in second row to line 101, Figure 2).
Regarding Claim 8, Liao et al. disclose the image sensing device according to claim 1, wherein: the pixel units further include an additional first pixel transistor located in a same row of the pixel array as one of the plurality of first pixel transistors, and one of the plurality of first upper signal lines is connected to the one of the plurality of first pixel transistors and the additional first pixel transistor (See transistor T1. The second end of the sensing element P1 may be electrically connected to a gate of the thin film transistor T1 and a second end of the thin film transistor T2. The gate of the thin film transistor T1 may be electrically connected to the second end of the sensing element P1 and the second end of the thin film transistor T2. A first end of the thin film transistor T1 may be electrically connected to the power line 104. For example, the power line 104 may provide a VDD voltage to the thin film transistor T1, but not limited thereto. A second end of the thin film transistor T1 may be electrically connected to a first end of the thin film transistor T3. The thin film transistor T1 may be used as an amplification transistor to amplify the signal sensed by the sensing element P1, but not limited thereto., Paragraphs 0031-0035; Figures 1-3).
In regard to Claim 9, Liao et al. disclose the image sensing device according to claim 1, further comprising: a plurality of first lower signal lines (Signal lines 124, Paragraph 0043; Figure 3) respectively connected to the plurality of first upper signal lines (102 and 106 connected to 124, Figure 3), wherein a first control signal for controlling a first pixel transistor is provided to a plurality of first pixel transistors located in an arbitrary row of the pixel array through an arbitrary first lower signal line and an arbitrary first upper signal line that is located in the arbitrary row of the pixel array and connected to an arbitrary first lower signal line (The signal line 1101 to the signal line 1104 and the pad 1161 to the pad 1164 may be electrically connected to one of the test pads 118 through thin film transistors TR in different transistor rows, and one of the test pads 118 may be electrically connected to four signal lines. The pad 1161 to the pad 1164 may be connected between the test pad 118 and the sensing units SU, and the test pad 118 may be electrically connected to the sensing units SU. Furthermore, the number of the pads 116 may be greater than the number of the test pads 118.The thin film transistors TR in different transistor rows can be turned on by transmitting switch signals through different signal lines 124, and the test signals can be transmitted to the corresponding sensing units SU through the pads 116, thus the function of the sensing units SU can be checked through the test pads 118., Paragraphs 0040-0047; Figure 3).
With regard to Claim 10, Liao et al. disclose the image sensing device according to claim 1, wherein: the first test line (1101) is located below the first upper signal line (102), and is located in a same substrate as the first upper signal line (The signal lines 110 (test line 1101) may be extended from the sensing region AR to the non-sensing region PR. As shown in FIG. 3, one of the signal lines 110/1101 may be electrically connected to the corresponding one of the pads 116, and therefore the sensing units SU may be electrically connected to the pads 116. Therefore, the first test line is below the first upper signal line and is located in a same substrate (sensing region AR) as the first upper signal line, Paragraphs 0041-0042; Figure 3).
Regarding Claim 11, Liao et al. disclose the image sensing device according to claim 1, wherein the pixel array includes a first substrate and a second substrate that are disposed to overlap each other (An electronic device 10 of this embodiment may include the substrate 100, the substrate 100 may include a sensing region AR (also referred to as an active region or a display region) and a non-sensing region PR (also referred to as a peripheral region), and the non-sensing region PR. The non-sensing region PR may surround the sensing region AR, Paragraphs 0026, 0041-0043; Figures 1-3).
4.) Allowable Subject Matter
i.)
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
ii.)
Claims 12-19 are allowed.
The following is an examiner’s statement of reasons for allowance:
In regard to independent Claim 12, the closest prior-art of record fails to teach or reasonably disclose the combination of the limitations to the claim that includes, “An image sensing device, comprising:
a pixel array located in a first substrate layer and configured to receive incident light and generate photocharge in response to the incident light;
a first upper signal line connected to the plurality of first pixel transistors and located in the first substrate layer;
a first test transistor connected to the first lower signal line and a first test pad,
wherein the first test line, the first test transistor and the first test pad are provided to test the plurality of first pixel transistors, and wherein
during a sensing operation, a first control signal for the first pixel transistor is provided to the plurality of first pixel transistors through the first lower signal line and the first upper signal line, and
during a test operation, a first test signal provided through the first test pad is provided to the plurality of first pixel transistors without passing through the first lower signal line.”
Dependent Claims 13-19 are also allowed due to their dependence on allowed independent claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRITHAM DAVID PRABHAKHER whose telephone number is (571)270-1128. The examiner can normally be reached Monday to Friday 8:00 am to 5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at 5712727372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Pritham David Prabhakher
Patent Examiner
Pritham.Prabhakher@uspto.gov
/PRITHAM D PRABHAKHER/Primary Examiner, Art Unit 2638