DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is a response to the amendment filed January 12, 2026. Claim 1 has been canceled by the applicant. Newly claims 2-24 are pending in the application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 9,996,284. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims [cited as line numbers] teaches the instants claims as follows:
As per claim 2:
The patent claim 1 teaches a memory system configured to communicate with a host memory controller [lines 1-3, memory accessing by the memory controller], comprising: a volatile memory (VM) subsystem including at least two VM modules respectively coupled to a first VM channel and a second VM channel [lines 7-21; first and second volatile memories coupled to the first and second memory channels respectively] ; a non-volatile memory (NVM) subsystem including a NVM controller and one or more NVM elements [lines 22-25; non-volatile memory element and controller]; and an interface couplable to the host memory controller and coupled to both the VM subsystem and the NVM subsystem, lines 4-22, an interface is coupled to the memory controller and the memory subsystem], wherein the interface is coupled to the NVM system via a common signal bus, and configured to access two or more independent memory channels that include the first VM channel and the second VM channel, the first VM channel via a first set of data, address and control signal lines, and the second VM channel via a second set of data, address and control signal lines, wherein the interface is operable to: receive from any one of the host memory controller, the VM subsystem, or the NVM subsystem a first set of signals selected from data, address signals, and control signals [see again lines 4-22, address, data and control signal lines are being used in coupling the interface to the memory subsystem and the memory controller]; monitor the first VM channel and the second VM channel to detect one or more memory access operations from the host memory controller to at least one memory address of the first VM module or the second VM module [lines 23-27]; generate, in correspondence with the first set of signals, a second set of signals selected from data, address signals, and control signals [lines 28-29; e.g., capturing a copy of data].
The patent claim 1 does not explicitly teaches 1) the interface include a memory controller and a switch for carrying out the above-mentioned bus monitoring and data capturing operation, and 2) the operation of transmitting the second set of signals to the NVM controller of the NVM subsystem.
Still an interface having a memory controller and a switch has been known and common practiced in the art prior to the effective filing date of the claimed invention [Official Notice is hereby taken]. Accordingly, it would have been obvious to one having ordinary skill in the art prior to the effective filing data of the claimed invention to employ a well-known interface, having a memory controller and a switch in the patent claim 1 system for performing the above-mentioned bus monitoring and data capturing operation, instead of the patent claim 1 non-volatile memory controller. It is a matter of design choice and the tradeoffs for doing so would have been readily recognized by one having ordinary skill in the art. Furthermore, the patent claim 2 teaches the claimed limitation of transmitting the second set of signals to the NVM controller of the NVM subsystem [i.e., storing the captured copy of data …in the at least one non-volatile memory element]. Accordingly, it would have been obvious to one having ordinary skill in the art to obtain the memory system of the instant claim 2 using the teaching of patent claims 1 and 2.
For claims 3-24:
Similarly to the above, the further claimed limitations can also be found in the patent claims 2-15
Claims 2-24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 9,436,600. Although the claims at issue are not identical, they are not patentably distinct from each other because the each of the claimed elements is an implementation of the patent operating steps [cited as line numbers in the parentheses]:
As per claim 2:
The patent claim 1 teaches operating steps that are carried out by a memory system configured to communicate with a host memory controller [lines 1-3, a memory access by a memory controller]], comprising: a volatile memory (VM) subsystem including at least two VM modules respectively coupled to a first VM channel and a second VM channel [lines 7-21; first and second volatile memory modules and the associated volatile memory channels] ; a non-volatile memory (NVM) subsystem including a NVM controller and one or more NVM elements [lines 22-25; non-volatile memory modules and the associated controller]; an interface couplable to the host memory controller and coupled to both the VM subsystem and the NVM subsystem, lines 4-6, the interface for coupling the memory subsystem to the memory controller is disclosed]
Clearly, each of the claimed elements in the instant claim is an implementation of the corresponding operating step of the patent claim 1, except that the patent claim 1 does not explicitly teaches 1) the interface include a memory controller and a switch, and 2) the operation of transmitting the second set of signals to the NVM controller of the NVM subsystem.
Still an interface having a memory controller and a switch has been known and common practiced in the art prior to the effective filing date of the claimed invention [Official Notice is hereby taken]. Accordingly, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to employ a well-known interface, having a memory controller and a switch, in the place of instant claim 2 switch. Furthermore, the patent claim 2 teaches the claimed limitation of transmitting the second set of signals to the NVM controller of the NVM subsystem [i.e., storing the captured copy of data …in the at least one non-volatile memory element]. Accordingly, it would have been obvious to one having ordinary skill in the art to obtain the memory system of the instant claim 2 using the teaching of patent claims 1 and 2.
For claims 3-24:
Similarly to the above, the further claimed limitations can also be found in the patent claims 2-25
Claims 2-24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-22 of U.S. Patent No. 10,719,246. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims [cited as line numbers] teaches the instant claims as follows:
As per claim 2:
The patent claim 1 teaches the memory system configured to communicate with a host memory controller [lines 1-2, memory system couplable to a host memory controller], comprising: a volatile memory (VM) subsystem including at least two VM modules respectively coupled to a first VM channel and a second VM channel [lines 3-5; first and second volatile memories coupled to the first and second memory channels respectively] ; a non-volatile memory (NVM) subsystem including a NVM controller and one or more NVM elements [lines 6-8; non-volatile memory element and controller]; and an interface couplable to the host memory controller and coupled to both the VM subsystem and the NVM subsystem, lines 9-10, an interface is coupled to the memory controller and the memory subsystem], wherein the interface is coupled to the NVM system via a common signal bus, and configured to access two or more independent memory channels that include the first VM channel and the second VM channel, the first VM channel via a first set of data, address and control signal lines, and the second VM channel via a second set of data, address and control signal lines, wherein the interface is operable to: receive from any one of the host memory controller, the VM subsystem, or the NVM subsystem a first set of signals selected from data, address signals, and control signals [lines 12-14]; monitor the first VM channel and the second VM channel to detect one or more memory access operations from the host memory controller to at least one memory address of the first VM module or the second VM module [lines 15-19]; generate, in correspondence with the first set of signals, a second set of signals selected from data, address signals, and control signals [lines 20-22] and, transmit the second set of signals to the NVM controller of the NVM subsystem [lines 23-24].
The patent claim 1 does not explicitly teaches that the interface include a memory controller and a switch.
Still an interface having a memory controller and a switch has been known and common practiced in the art prior to the effective filing date of the claimed invention [Official Notice is hereby taken]. Accordingly, it would have been obvious to one having ordinary skill in the art prior to the effective filing data of the claimed invention to employ a well-known interface, having a memory controller and a switch in the patent claim 1 system for performing the above-mentioned bus monitoring and data capturing operation, instead of the patent claim 1 non-volatile memory controller. It is a matter of design choice and the tradeoffs for doing so would have been readily recognized by one having ordinary skill in the art.
For claims 3-24:
Similarly to the above, the further claimed limitations can also be found in the patent claims 2-15
Allowable Subject Matter
Claims 2-24 would be allowable over the prior art of record when a terminal disclaimer is filed to overcome the above-mentioned obvious-type double patenting rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Auemhammer et al., US 2009/0144505, teaches a bus snooper in a memory hierarchy system having two level caches [see para. 0082].
McWilliams et al., US 5,355,467, teaches snooping second level cache for data write back to main memory [see the abstract].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HIEP T NGUYEN/Primary Examiner, Art Unit 2137
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