DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty and different boundaries “wherein a first material of the mitigation layer is less affected by an orientation of the wiring layer than a second material of a portion of the metal layer located closest to the wiring layer.
The claim is indefinite because of the following:
“Less affected” is not clear with what is being affected. Additionally, it is unclear “the portion of a metal layer”, what portion of the metal will affect more or less of the mitigation layer (i.e. will another portion of the metal layer affect more).
Appropriate clarification and/or correction are/is required within the metes and bounds of the claimed invention.
The examiner will interpret the claims as the crystallographic orientation of the mitigation layers do not change based on the wiring layer and the metal layer (i.e. the examiner will consider the materials of the layers as disclosed in the invention).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 10-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Faust et al. US 2015/0145125.
PNG
media_image1.png
500
650
media_image1.png
Greyscale
Faust et al. US 2015/0145125
Regarding claim 1, Faust et al. Fig. 1 and [0020]-[0028] disclose a semiconductor element comprising:
an element body 1 [0020] including an element obverse surface 2 [0020] facing a first side in a thickness direction;
a wiring layer 3 [0020] formed on the element obverse surface 2 and electrically connected to the element body 1;
an insulating layer 4´ Fig. 1 [0021]-[0023] covering the element obverse surface 2 and the wiring layer 3, and including a first opening (annotated above) overlapping with the wiring layer 3 as viewed in the thickness direction;
a surface protection film 5 [0021] covering the insulating layer 4´, and including a second opening (annotated above) overlapping with the wiring layer 3 and the first opening as viewed in the thickness direction;
a metal layer 7 [0023] overlapping with the first opening and the second opening, and also overlapping with the surface protection film 5 as viewed in the thickness direction, and
a mitigation layer 6 [0023] provided between the wiring layer 3 and the metal layer 7,
wherein a first material of the mitigation layer 6 (e.g. Ti) is less affected by an orientation of the wiring layer 3 (e.g. Al) than a second material of a portion of the metal layer 7 (e.g. copper-base) located closest to the wiring layer 3.
Regarding claim 2, Faust et al. Fig. 1 and [0020]-[0028] disclose the semiconductor element according to claim 1, wherein the wiring layer contains Al [0020].
Regarding claim 3, Faust et al. Fig. 1 and [0020]-[0028] disclose the semiconductor element according to claim 1, wherein the mitigation layer 6 includes a portion located between the metal layer 7 and the surface protection film 5.
Regarding claim 4, Faust et al. Fig. 1 and [0020]-[0028] disclose the semiconductor element according to claim 3, wherein the first material contains TiW [0023].
Regarding claim 10, Faust et al. Fig. 1 and [0020]-[0028] disclose the semiconductor element according to claim 1, wherein a shape [0022] of the first opening (annotated above) and a shape of the second opening (annotated above) are each similar to a shape of the metal layer 7 as viewed in the thickness direction.
Regarding claim 11, Faust et al. Fig. 1 and [0020]-[0028] disclose the semiconductor element according to claim 1, wherein the second opening (annotated above) is enclosed (e.g. surrounded) by the first opening (annotated above) as viewed in the thickness direction.
Regarding claim 12, Faust et al. Fig. 1 and [0020]-[0028] disclose the semiconductor element according to claim 1, wherein the surface protection film 5 contains polyimide resin [0021].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Faust et al. as applied to claim 1 above, and further in view of Haga et al. US 2017/0294400.
Regarding claim 7, Faust et al. Fig. 1 and [0020]-[0028] disclose the semiconductor element according to claim 1, but do not expressly disclose wherein the metal layer 7 includes: a first layer containing Ni; and a second layer in contact with a surface of the first layer on a side that the element obverse surface faces, and containing Pd.
Haga et al. Fig. 4 and [0037]-[0052] teach a semiconductor element comprising a wiring layer 23 [0039], an insulating layer 30 [0045], a surface protection film 17 [0047] and a laminated metal layer 39 [0049]-[0052] including a first layer containing Ni; and a second layer in contact with a surface of the first layer on a side that the element obverse surface faces, and containing Pd.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Haga et al. [0005] in the semiconductor element of Faust et al. for the purpose of providing a semiconductor device which is low in cost and enables satisfactory conduction reliability of a pad to be secured.
Regarding claim 8, Faust et al. in view of Haga et al. teach the semiconductor element according to claim 7. Haga et al. teach wherein the metal layer 39 further includes a third layer in contact with a surface of the second layer on the side that the element obverse surface faces, and containing Au [0052].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Faust et al.
Regarding claim 9, Faust et al. Fig. 1 and [0020]-[0028] disclose the semiconductor element according to claim 1, but do not expressly disclose wherein the metal layer has a circular shape as viewed in the thickness direction.
However, the Applicant has not presented persuasive evidence that the claimed “wherein the metal layer has a circular shape as viewed in the thickness direction” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the metal layer having a circular shape as viewed in the thickness direction). Therefore, no rationale is given that the invention will not function without a metal layer having a circular shape as viewed in the thickness direction. Thus, the claimed wherein the metal layer has a circular shape as viewed in the thickness direction is not critical to the invention.
The Examiner would like to note that MPEP §2144.04.IV(B) guideline, where change of shape is a Legal Precedent as Source of Supporting Rationale. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
Faust et al. further suggests in [0022] that those skilled in the art will recognize that there is an aperture formed in the dielectric layer to expose at least a portion of bond pad 3. The aperture can be any shape and size.
In view of the above, as there is no persuasive evidence that the particular configuration of “wherein the metal layer has a circular shape as viewed in the thickness direction” is significant, and Faust et al.’s suggestion of those skilled in the art will recognize that the opening can be any shape and size; the claimed limitation of “wherein the metal layer has a circular shape as viewed in the thickness direction” is a matter of choice which a person of ordinary skill in the art would have found obvious as per MPEP §2144.04.IV(B) guideline. Therefore, the claimed limitation of “wherein the metal layer has a circular shape as viewed in the thickness direction” is not patentable over Faust et al.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Faust et al. as applied to claim 1 above, and further in view of Tanaka et al. US 2021/0257274.
Regarding claim 13, Faust et al. Fig. 1 and [0020]-[0028] disclose the semiconductor element according to claim 1, but do not expressly disclose the semiconductor element further comprising a reverse-surface electrode electrically connected to the element body, wherein the element body includes an element reverse surface facing away from the element obverse surface in the thickness direction, and the reverse-surface electrode is arranged on the element reverse surface.
Tanaka et al. Fig. 3 and [0062] teach a reverse face electrode 22 electrically connected to an element body 10, wherein the element body 10 includes an element reverse surface facing away 10B from the element obverse surface 10A in the thickness direction, and the reverse-surface electrode 22 is arranged on the element reverse surface 10B.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Tanaka et al. [0002] in the semiconductor element of Faust et al. for the purpose of including a switching circuit, such as a MOSFET and an IGBT.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. US 2021/0257274 in view of Faust et al.
Regarding claim 14, Tanaka et al. Fig. 7 and [0046]-[0122] disclose a semiconductor device comprising: a semiconductor element A10;
a conductive support member 512, 521 [0100] supporting the semiconductor element and electrically connected to the semiconductor element Fig. 22;
a connecting member 61 [0099] bonded to the metal layer of the semiconductor element and the conductive support member [0108]-[0110]; and
a sealing resin 70 covering the semiconductor element A10, the connecting member 61, and a portion of the conductive support member 521 Figs. 22-23.
Tanaka et al. do not expressly disclose the semiconductor element according to claim 1.
However, Faust et al. Fig. 1 and [0020]-[0028] disclose a semiconductor element (e.g. pad structure for a semiconductor chip) with good adhesion between bond pad and metal layer [0023], as well as increased wettability and bond ability of the structure [0026] comprising: an element body 1 [0020] including an element obverse surface 2 [0020] facing a first side in a thickness direction; a wiring layer 3 [0020] formed on the element obverse surface 2 and electrically connected to the element body 1; an insulating layer 4´ Fig. 1 [0021]-[0023] covering the element obverse surface 2 and the wiring layer 3, and including a first opening (annotated above) overlapping with the wiring layer 3 as viewed in the thickness direction; a surface protection film 5 [0021] covering the insulating layer 4´, and including a second opening (annotated above) overlapping with the wiring layer 3 and the first opening as viewed in the thickness direction; a metal layer 7 [0023] overlapping with the first opening and the second opening, and also overlapping with the surface protection film 5 as viewed in the thickness direction, and a mitigation layer 6 [0023] provided between the wiring layer 3 and the metal layer 7, wherein a first material of the mitigation layer 6 (e.g. Ti) is less affected by an orientation of the wiring layer 3 (e.g. Al) than a second material of a portion of the metal layer 7 (e.g. copper-base) located closest to the wiring layer 3.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Faust et al. in the semiconductor device of Tanaka et al. to provide a more reliable device structure.
Regarding claim 15, Tanaka et al. in view of Faust et al. teach the semiconductor device according to claim 14. Tanaka et al. [0108] teach wherein the connecting member 61 is a bonding wire containing Cu.
Allowable Subject Matter
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the prior art neither anticipates nor renders obvious in the context of the claims, wherein the mitigation layer includes a portion located between the wiring layer and the insulating layer. Claim 6 depends from claim 5.
Although various prior art references disclose several individual limitations in the claims, these references, and their combinations, neither anticipate nor render obvious the above identified limitation(s), as structured and interrelated in the context of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898