Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 11-12, and 17-18 are rejected under 35 U.S.C. 102a1 as being anticipated by Varadarajan (US 20220319627).
Regarding claim 17, Varadarajan teaches:
A device, comprising: a reconfiguration memory; (see fig. 5, memory M1-M3 (404A-404C) able to be reconfigured by repair bits (408A-408C). And see para. 2: the circuit provides redundant rows and/or columns that are used to reconfigure the memory to use redundant rows and/or columns instead of the defective rows and/or columns in the memory block. The process of reconfiguring the memory to use redundant rows and/or columns instead of defective rows and/or columns is referred to as physical memory repair.)
a module comprising: elements; and a reconfiguration register; (see fig. 5, repair bits 408A-408C considered to be in a reconfiguration register, also see other elements depicted).
a repair controller configured to receive a stream of test data associated with the module; (see para. 36: To perform memory repairs in the memory repair scenario 400, the BIST unit 202 tests the memory units 404A-404C to determine if memory repair is needed. In response to the test from BIST unit, the local compare circuits 405A-405C compute the error from the respective memory units 404A-404C. The local compare circuits 405A-405C are instances of the local compare circuit 255 of FIG. 2B to compute the error from the memory units 404A-404C. The errors from diverse memory units are aligned to a unified format and merged together by the align and merge circuit 410. The cumulative repair information from the align and merge circuit 410 is provided to a repair analysis circuit 414 via an OR gate 412.)
and a positional codec system, comprising: a protocol engine configured to receive the stream of test data from the repair controller; a detection circuit configured to identify first care data at a first position in the stream of test data corresponding to a first element of the elements in the module; (See para. 37: The output of the repair analysis circuit 414 is also provided to a fuse reconfiguration circuit 416, which performs the inverse operation of align and merge circuit 410 to reconfigure the repair analysis output in the unified format (converted by align and merge circuit 410) back to the target memory repair architecture. The fuse reconfiguration circuit 416 then writes cumulative repair information (a repair signature for each of the memory units 404A-404C) to shadow fuse registers 422A-422C.)
and a first access module configured to store the first care data and the first position in the reconfiguration memory, wherein: the repair controller is configured to program the reconfiguration register using the first care data to set a parameter associated with the first element or designate a second element as a replacement for the first element. (see para. 38: After the BIST unit 202 completes testing on all memory units 404A-404C, the newly identified memory repair signature from the shadow fuse registers 422A-422C is stored into the memory repair registers 408A-408C by shifting out through the other input of the multiplexer 424. The other input to the multiplexers 420A-420C are configured to form a shift register by passing the repair information from adjacent shadow fuse registers for each of the memory units 404A-404C. As shown, the output from the shadow fuse register 422A (corresponding to the memory unit 404A) is fed into a multiplexer 424, where the output of the multiplexer 424 is provided to the memory unit 404C. While the data from shadow fuse register 422A is shifted into memory repair register 408C, the data stored in the shadow fuse registers 420C and 420B would have also been shifted into 420B and 420A, respectively. This process continues till the repair registers 408A, 408B and 408C are initialized with the data from the shadow fuse registers 422A, 422B and 422C respectively.) The first position is effectively stored because the positions of individual bits of the repair signatures (considered to be sets of care data) is maintained as they are shifted along the scan chain and into the reconfigurable memory.
Regarding claim 18, Varadarajan teaches the device of claim 17. Varadarajan further teaches:
wherein: the positional codec system comprises: a memory storing previous reconfiguration data associated with the device loaded from the reconfiguration memory, wherein: (see para. 34: During the system power-up or initialization sequence before any functional or test operations on the memory units, shadow fuse registers 422A-422C are reset/cleared and the memory repair data (possibly from prior test sessions) stored in FuseROM or a similar non-volatile memory is serially loaded into the corresponding memory repair registers 408A-408C through the input 425A and multiplexer 424. Simultaneously, the corresponding shadow fuse registers 422A-422C are also serially initialized with the same memory repair data through the input 425B and multiplexers 420A-420C. Thus, at the end of system initialization, the shadow fuse registers 422A-422C has identical data as the corresponding memory repair register 408A-408C.)
the detection circuit is configured to identify second care data at a second position in the stream of test data corresponding to a third element of the elements in the module; (see para. 38: After the BIST unit 202 completes testing on all memory units 404A-404C, the newly identified memory repair signature from the shadow fuse registers 422A-422C is stored into the memory repair registers 408A-408C by shifting out through the other input of the multiplexer 424. The other input to the multiplexers 420A-420C are configured to form a shift register by passing the repair information from adjacent shadow fuse registers for each of the memory units 404A-404C. As shown, the output from the shadow fuse register 422A (corresponding to the memory unit 404A) is fed into a multiplexer 424, where the output of the multiplexer 424 is provided to the memory unit 404C. While the data from shadow fuse register 422A is shifted into memory repair register 408C, the data stored in the shadow fuse registers 420C and 420B would have also been shifted into 420B and 420A, respectively. This process continues till the repair registers 408A, 408B and 408C are initialized with the data from the shadow fuse registers 422A, 422B and 422C respectively.)
and a second access module configured to identify an entry in the memory corresponding to the second position, wherein:
the first access module is configured to store the second care data and the second position in the reconfiguration memory responsive to the second access module not identifying the entry in the memory corresponding to the second position. (see para. 37: The output of the repair analysis circuit 414 is also provided to a fuse reconfiguration circuit 416, which performs the inverse operation of align and merge circuit 410 to reconfigure the repair analysis output in the unified format (converted by align and merge circuit 410) back to the target memory repair architecture. The fuse reconfiguration circuit 416 then writes cumulative repair information (a repair signature for each of the memory units 404A-404C) to shadow fuse registers 422A-422C. The OR gates 418A-418C merges the previously stored repair signature from the shadow fuse register (either from the power-up initialization or prior test sessions) with the new repair signature from the fuse reconfiguration unit 416 and the multiplexers 420A-420C configures the shadow fuse registers to store back the new merged repair signature.) It would be obvious to one of ordinary skill in the art, that if there was no previous reconfiguration data in the memory corresponding to a position, the value loaded into the corresponding shadow fuse register position would be 0. It is well known that an OR operation performed on zeros and one other bitstring would equal the other bitstring. Therefore, in the case that there was no previous repair signature corresponding to the position (only zeros stored in the shadow fuse register), Varadarajan’s system would perform the OR operation on the new care data and the 0s, which would result in exactly the new data, which would subsequently be stored into the shadow fuse registers and then loaded to the reconfiguration memory.
Claims 1-2 and 11-12 correspond to claims 17-18 and 17-18 (respectively), and are rejected accordingly.
Regarding claim 3, Varadarajan teaches the method of claim 2. Varadarajan further teaches:
responsive to the previous reconfiguration data comprising an entry associated with the second position, sending a third write command to overwrite the second care data in an entry in the reconfiguration memory associated with the second position. (see para. 37: The output of the repair analysis circuit 414 is also provided to a fuse reconfiguration circuit 416, which performs the inverse operation of align and merge circuit 410 to reconfigure the repair analysis output in the unified format (converted by align and merge circuit 410) back to the target memory repair architecture. The fuse reconfiguration circuit 416 then writes cumulative repair information (a repair signature for each of the memory units 404A-404C) to shadow fuse registers 422A-422C. The OR gates 418A-418C merges the previously stored repair signature from the shadow fuse register (either from the power-up initialization or prior test sessions) with the new repair signature from the fuse reconfiguration unit 416 and the multiplexers 420A-420C configures the shadow fuse registers to store back the new merged repair signature.) The new repair signature (new care data) is ORed with the old repair signature, and the merged repair signature (including elements of the new repair signature) overwrites previously stored data in the shadow registers and is subsequently loaded to the reconfigurable memory.
Regarding claim 4, Varadarajan teaches the method of claim 2. Varadarajan further teaches:
performing a logical OR on the second care data and previous care data in an entry in the reconfiguration memory associated with the second position; and sending a third write command to overwrite the entry in the reconfiguration memory associated with the second position based on the logical OR. (see para. 37: The output of the repair analysis circuit 414 is also provided to a fuse reconfiguration circuit 416, which performs the inverse operation of align and merge circuit 410 to reconfigure the repair analysis output in the unified format (converted by align and merge circuit 410) back to the target memory repair architecture. The fuse reconfiguration circuit 416 then writes cumulative repair information (a repair signature for each of the memory units 404A-404C) to shadow fuse registers 422A-422C. The OR gates 418A-418C merges the previously stored repair signature from the shadow fuse register (either from the power-up initialization or prior test sessions) with the new repair signature from the fuse reconfiguration unit 416 and the multiplexers 420A-420C configures the shadow fuse registers to store back the new merged repair signature.) Data in the shadow fuse registers is subsequently be stored to the reconfigurable memory.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-10, 13-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Varadarajan in view of Dempsey (US 2007/0168836).
Regarding claim 14, Varadarajan teaches the positional codec system of claim 12. Varadarajan further teaches wherein:
The previous reconfiguration data comprises: previous care data entries; and positions associated with the previous care data entries. (see para. 34: During the system power-up or initialization sequence before any functional or test operations on the memory units, shadow fuse registers 422A-422C are reset/cleared and the memory repair data (possibly from prior test sessions) stored in FuseROM or a similar non-volatile memory is serially loaded into the corresponding memory repair registers 408A-408C through the input 425A and multiplexer 424. Simultaneously, the corresponding shadow fuse registers 422A-422C are also serially initialized with the same memory repair data through the input 425B and multiplexers 420A-420C. Thus, at the end of system initialization, the shadow fuse registers 422A-422C has identical data as the corresponding memory repair register 408A-408C.). The position previous care entries are stored in corresponds to the position associated with the previous care entries.
However, Varadarajan does to explicitly teach: and the memory comprises: a lookup table storing the previous care data entries and the positions associated with the previous care data entries.
In the analogous art of repair bits for memory, Dempsey teaches:
and the memory comprises: a lookup table storing the previous care data entries and the positions associated with the previous care data entries.
(see para. 40, fig. 4a, and fig. 4b: the firmware stores a lookup table to associate any combination of the following with each other: a cache location/bit to be repaired, a cache line/word including the cache location/bit to be repaired, a repair location/bit, or a column of the cache including the cache location/bit to be repaired. As discussed below, a lookup table potentially assists in the repairing of cache locations upon accesses to the cache. Also see para. 28: Ways within repair cache 430 are associated with the logically viewable columns/vertical stripes in cache 405.) The combination of the repair cache 430 and the repair lookup table 460, both stored in the reconfigurable memory, is considered to be a lookup table storing previous care data (repair bits) and the positions associated with the previous care data (the column of the cache including the cache location/bit to be repaired, which is also the column the repair bit is stored in).
It would be obvious to one of ordinary skill in the art to incorporate the repair cache/LUT structure taught by Dempsey into the system for providing incremental repair taught by Varadarajan, to allow for benefits such as: using a lookup table assists in the repairing (para. 40). Further, it is well known in the art that using lookup tables to retrieve data allows for benefits such as fast and efficient data retrieval.
Claim 6 corresponds to claim 14, and is rejected accordingly.
Regarding claim 16, Varadarajan teaches the positional codec system of claim 11. Varadarajan teaches: a memory storing previous reconfiguration data associated with the device loaded from the reconfiguration memory, (see fig. 4A, repair register 408A-C and shadow fuse registers 422A-422B both store previous reconfiguration data associated with the device, loaded from the reconfiguration memory).
However, Varadarajan does not explain how the repair bits in the repair register 408A-C are used for a read request.
Dempsey further explains the process of using repair bits, teaching:
the protocol engine is configured to receive a read request associated with a second position corresponding to a second element of the device; and a second access module configured to: responsive to a first entry being present in the memory corresponding to the second position, send second care data associated with the first entry for the read request; and responsive to the first entry not being present in the memory corresponding to the second position, sending null data for the read request. (see para. 59: As stated above, upon a read to a cache line including a bad bit, a repair bit [care data] associated with the column of the bad bit is read from the repair bit and replaces the bad bit upon fulfilling the read request. As an example, assume that processor 505 makes a read request referencing main memory address 566, which is mapped to set 540. Cache 510 includes a copy of main memory location 566 in line 521. Repair module 560 determines that bit 545 is to be repaired. As an illustrative example, it is assumed that repair logic 560 had previously determined that bit 545 was a failed bit and created an entry in a table to associate that bad bit 545 is to be repaired by repair bit 557. Cache line 521 is then read out of cache 510 and the value from bad bit 545 is replaced with the value stored in repair bit 557. In the end, microprocessor 505 receives a valid copy of main memory location 566 from cache 510, as bad bit 545 was replaced with valid information from repair bit 557.) Clearly the described process is in response to a read request, checking each for bit to-be-read if there is associated care data (a repair bit). If there is, the care data (repair bit) is provided. While Dempsy does not explicitly teach what happens if a read request references a place in memory with no entry present, it is well known and would be obvious to one of ordinary skill in the art to return a null value, signifying there was no data entry associated with the read request.
It would be obvious to one of ordinary skill in the art to incorporate the repair cache/LUT structure taught by Dempsey into the system for providing incremental repair taught by Varadarajan, to allow for benefits such as: using a lookup table assists in the repairing (para. 40). Further, it is well known in the art that using lookup tables to retrieve data allows for benefits such as fast and efficient data retrieval.
Claim 9 corresponds to claim 16, and is rejected accordingly.
Regarding claim 10, the combination of Varadarajan and Dempsey teaches the method of claim 9. Dempsey further teaches:
loading a memory with previous reconfiguration data associated with the device from the reconfiguration data; accessing the memory to determine whether a second entry corresponding to the first entry is present in the memory; and responsive to the second entry being present in the memory, retrieving the second care data from the second entry. (see para. 59: As stated above, upon a read to a cache line including a bad bit, a repair bit [care data] associated with the column of the bad bit is read from the repair bit and replaces the bad bit upon fulfilling the read request. As an example, assume that processor 505 makes a read request referencing main memory address 566, which is mapped to set 540. Cache 510 includes a copy of main memory location 566 in line 521. Repair module 560 determines that bit 545 is to be repaired. As an illustrative example, it is assumed that repair logic 560 had previously determined that bit 545 was a failed bit and created an entry in a table to associate that bad bit 545 is to be repaired by repair bit 557. Cache line 521 is then read out of cache 510 and the value from bad bit 545 is replaced with the value stored in repair bit 557. In the end, microprocessor 505 receives a valid copy of main memory location 566 from cache 510, as bad bit 545 was replaced with valid information from repair bit 557.) The second entry (storing care data) corresponding to the first entry would be the repair bit in the repair cache associated with the bit from the read request.
It would be obvious to one of ordinary skill in the art to incorporate the repair cache/LUT structure taught by Dempsey into the system for providing incremental repair taught by Varadarajan, to allow for benefits such as: using a lookup table assists in the repairing (para. 40). Further, it is well known in the art that using lookup tables to retrieve data allows for benefits such as fast and efficient data retrieval.
Regarding claim 19, Varadarajan teaches the device of claim 18. Varadarajan further teaches wherein:
The previous reconfiguration data comprises: previous care data entries; and positions associated with the previous care data entries. (see para. 34: During the system power-up or initialization sequence before any functional or test operations on the memory units, shadow fuse registers 422A-422C are reset/cleared and the memory repair data (possibly from prior test sessions) stored in FuseROM or a similar non-volatile memory is serially loaded into the corresponding memory repair registers 408A-408C through the input 425A and multiplexer 424. Simultaneously, the corresponding shadow fuse registers 422A-422C are also serially initialized with the same memory repair data through the input 425B and multiplexers 420A-420C. Thus, at the end of system initialization, the shadow fuse registers 422A-422C has identical data as the corresponding memory repair register 408A-408C.). The position previous care entries are stored in corresponds to the position associated with the previous care entries.
However, Varadarajan does not explicitly disclose that:
the memory comprises: a cache storing the previous care data entries according to a cache index; and a lookup table storing the positions associated with the previous care data entries linked by the cache index.
In the analogous art of repair bits in memory, Dempsey teaches:
the memory comprises: a cache storing the previous care data entries according to a cache index; and a lookup table storing the positions associated with the previous care data entries linked by the cache index. (see fig. 4a, 4b, and para. 48: As mentioned above, in one embodiment, module 450 may track which bit within cache 405 a repair bit in repair cache 430 is to repair. For example, in a lookup table, such as lookup table 460 illustrated in FIG. 4b, the repair bits, listed in column 465 [listed by some bit identifier, considered to be a cache index], are associated with the bits they repair in cache 405, which are listed as corresponding entries in column 470 [effectively describing the column/row location of the bit to be repaired]. Therefore, when an access references cache line 413 including locations 428 and 429, by checking lookup table 460 it is able to be determined that bits 428 and 429 are targeted to be repaired. In addition, table 460 includes the information that they are to be repaired by bits 438 and 439. Also see para. 28: Ways within repair cache 430 are associated with the logically viewable columns/vertical stripes in cache 405.) See that in fig. 4a, repair bits are stored in repair cache 430. Also see that the location of the bit they are repairing is stored in the lookup table.
It would be obvious to one of ordinary skill in the art to incorporate the repair cache/LUT structure taught by Dempsey into the system for providing incremental repair taught by Varadarajan, to allow for benefits such as: using a lookup table assists in the repairing (para. 40). Further, it is well known in the art that using lookup tables to retrieve data allows for benefits such as fast and efficient data retrieval.
Claims 5 and 13 correspond to claim 19, and are rejected accordingly.
Regarding claim 20, Varadarajan teaches the method of claim 17.
Dempsey teaches:
the positional codec system comprises: a dictionary storing the first care data based on a dictionary index, and the first access module is configured to store the dictionary index in an entry of the reconfiguration memory. (see fig. 4a, 4b, and para. 48: As mentioned above, in one embodiment, module 450 may track which bit within cache 405 a repair bit in repair cache 430 is to repair. For example, in a lookup table, such as lookup table 460 illustrated in FIG. 4b, the repair bits, listed in column 465 [listed by some bit identifier, considered to be a dictionary index], are associated with the bits they repair in cache 405, which are listed as corresponding entries in column 470 [effectively describing the column/row location of the bit to be repaired]. Therefore, when an access references cache line 413 including locations 428 and 429, by checking lookup table 460 it is able to be determined that bits 428 and 429 are targeted to be repaired. In addition, table 460 includes the information that they are to be repaired by bits 438 and 439. Also see para. 28: Ways within repair cache 430 are associated with the logically viewable columns/vertical stripes in cache 405. Also see para. 40: the firmware stores a lookup table to associate any combination of the following with each other: a cache location/bit to be repaired, a cache line/word including the cache location/bit to be repaired, a repair location/bit, or a column of the cache including the cache location/bit to be repaired. As discussed below, a lookup table potentially assists in the repairing of cache locations upon accesses to the cache.) While not explicitly stated, one of ordinary skill in the art would find it obvious that the lookup table would be stored in the reconfigurable memory. A dictionary is a well-known and obvious implementation of a lookup table in the art. The combination of the repair cache 430 and the repair lookup table 460, both stored in the reconfigurable memory, is considered to be a dictionary storing care data based on a dictionary index. As stated above, the lookup table (dictionary) is considered to be stored in the reconfigurable memory, so the dictionary indices are further considered to be stored in the reconfigurable memory.
It would be obvious to one of ordinary skill in the art to incorporate the repair cache/LUT (dictionary) structure taught by Dempsey into the system for providing incremental repair taught by Varadarajan, to allow for benefits such as: using a lookup table assists in the repairing (para. 40). Further, it is well known in the art that using lookup tables (or dictionaries) to retrieve data allows for benefits such as fast and efficient data retrieval.
Claims 7 and 15 correspond to claim 20, and are rejected accordingly.
Regarding claim 8, the combination of Varadarajan and Dempsey teaches the method of claim 7.
Dempsey further teaches:
Sending a command to store the dictionary to the reconfigurable memory. (see para. 40: the firmware stores a lookup table to associate any combination of the following with each other: a cache location/bit to be repaired, a cache line/word including the cache location/bit to be repaired, a repair location/bit, or a column of the cache including the cache location/bit to be repaired. As discussed below, a lookup table potentially assists in the repairing of cache locations upon accesses to the cache.) While not explicitly stated, one of ordinary skill in the art would find it obvious that the lookup table would be stored in the reconfigurable memory. A dictionary is a well-known and obvious implementation of a lookup table in the art. Therefore the section of the above citation: “the firmware stores a lookup table…” is considered to be a disclosure of sending a command to store the lookup table (dictionary) to the reconfigurable memory.
It would be obvious to one of ordinary skill in the art to incorporate the repair cache/LUT structure taught by Dempsey into the system for providing incremental repair taught by Varadarajan, to allow for benefits such as: using a lookup table assists in the repairing (para. 40). Further, it is well known in the art that using lookup tables to retrieve data allows for benefits such as fast and efficient data retrieval.
Conclusion
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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