Prosecution Insights
Last updated: October 27, 2026
Application No. 18/900,835

MEMORY ACCESS METHOD AND RELATED DEVICE

Non-Final OA §103
Filed
Sep 29, 2024
Priority
Mar 30, 2022 — CN 202210326125.8 +2 more
Examiner
BATAILLE, PIERRE MICHE
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Huawei Technologies Co., Ltd.
OA Round
3 (Non-Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1128 granted / 1216 resolved
+37.8% vs TC avg
Moderate +6% lift
Without
With
+6.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
13 currently pending
Career history
1241
Total Applications
across all art units

Statute-Specific Performance

§101
5.7%
-34.3% vs TC avg
§103
40.5%
+0.5% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1216 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 remain pending in the application under prosecution and have been reexamined. Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Response to Arguments Applicant's arguments filed 08/30/2026 have been fully considered but they are moot in view of new ground of rejection. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 6854039 B1 (STRONGIN et al) in view of US 20230007642 A1 (DECARREAU et al). With respect to claims 1, 15 and 20, STRONGIN teaches memory access method of a memory access apparatus, implemented by a first apparatus, the method comprising: a memory storing instructions; a transmission interface; and at least one processor in communication with the transmission interface and the memory, the at least one processor configured, upon execution of the instructions, to perform the method comprising: ((security check unit to receive physical address and the security attributes of a selected memory page security check unit coupled to perform method for providing access security for a memory used to store data arranged within multiple memory pages); receiving a first access request, wherein the first access request comprises an identity number, a first security check value, and first information comprising a first physical address (security check unit coupled to receive the physical address and the security attributes of the selected memory page wherein information include: secure execution mode; secure execution mode value representing a security attribute of the currently executing instruction; a base address with offset value, privilege security level; receiving a linear address produced during execution of an instruction and a security attribute of the instruction, wherein the instruction resides in a first memory page, wherein the linear address is used to access one or more paged memory data structures located in the memory to obtain a base address of a selected memory page and security attributes of the selected memory page); and determining an access permission of the second apparatus for the first physical address based on the first security check value and the second security check value (the security attribute of the instruction and the security attributes of the selected memory page to indicate whether or not the selected memory page is a secure page, therefore, to indicate the access is authorized; otherwise the security check unit to generate a fault signal dependent upon the security attributes of selected memory page and the additional security attribute of the selected memory page preventing access; using the security attributes of selected memory page and the additional security attribute of the selected memory page to generate a page fault indicating unauthorized-hardware initiated memory access, wherein the security check unit generates the fault signal dependent upon the security attributes of selected memory page and the additional security attribute of the selected memory page) [Abstract; Fig. 7; Fig. 14; Fig. 15; Col. 5, Line 30 to Col. 6, Line 24; Col. 10, Lines 13-41; Col. 16, Lines 6-42, Col. 13, Lines 6-40]. STRONGIN teaches memory access method comprising security check unit using the physical address to access one or more security attribute data structures located in the memory to obtain an additional security attribute of the selected memory page; using the received physical address of the selected memory page and access of one or more security attribute data structures located in the memory to obtain an additional security attribute of the selected memory page, i.e., determining permission, privilege level (Col. 13, Lines 6-40; Col. 5, Line 30 to Col. 6, Line 24; Col. 10, Lines 13-41). STRONGIN fails to specifically teach obtaining a second security check value through computation, the computation of the second security check value being based on the identity number and the first information. However, DECARREAU teaches method comprising: transmitting, from a base station, an indication of a sequence of identifier values for a user equipment through computation of an identifier value for the user equipment comprising: computing an identifier value based on one or more input parameter values and one or more mathematical functions used at the base station to compute an identifier value for the user equipment, wherein the computation of an identifier value may be at least partly based on a security key value derived at least partly from a secret key shared between the base station and the user equipment [Par. 0016; Par. 0019; Par. 0023: Par. 0035-0039]. DECARREAU teaches sending to a user equipment a base value (a first identifier value) for computation of an identifier value; and, in response to thereafter determining that computation based on the base value (the first identifier value) generating an identifier value computing a sequence of identifier values (second identifier value), the computation inputs including a security key (here referred to as KRNTI) derived from a secret key pre-shared between the user equipment (UE) and a home subscriber server (HSS), which secret key primarily used to authenticate the UE [Par. 0028-0030; Par. 0094-0099; Par. 0112-0113]. Therefore, it would have been obvious to one having at least ordinary skill in the art before, the effective filing of the instant application to combine the memory management unit for managing a memory storing data, as taught by STRONGIN, with computation of a second security check value being based on the identity number and a first information of DECARREAU, in order to incorporate identifier values for the user equipment into one or more control channel transmissions specific to the user equipment, as taught by DECARREAU [Par. 0016]. With respect to claims 2 and 16, STRONGIN and DECARREAU teach memory access method, wherein the identity number identifies the first apparatus, or the identity number identifies the second apparatus (security attribute of the selected memory page to include a security context identification (SCID) value indicating a security context level of the selected memory page, the security attribute of the current instruction may include an SCID value indicating a security context level of a memory page containing the current instruction) [SRRONGIN’s Fig. 8; Abstract; Col. 4, Line 46 to Col. 5, Line 10] [computation inputs including a security key (here referred to as KRNTI) derived from a secret key pre-shared between the user equipment (UE) and a home subscriber server (HSS), which secret key primarily used to authenticate the UE (DECARREAU’s Par. 0028-0030; Par. 0094-0099)]. With respect to claims 3 and 17, STRONGIN and DECARREAU teach memory access method, wherein before the receiving the first access request from the second apparatus, the method further comprises: receiving a physical address application request from the second apparatus, wherein the physical address application request comprises the identity number; generating a first key for the identity number; and sending a first response to the physical address application request to the second apparatus, wherein the first response comprises the first security check value and the first information, and the first security check value is obtained through computation based on the first key (security check unit uses the physical address to access one or more security attribute data structures located in the memory to obtain a security attribute of the selected memory page, compares a numerical value conveyed by a security attribute of the current instruction to a numerical value conveyed by the security attribute of the selected memory page, and produces an output signal dependent upon a result of the comparison, the memory management unit to access selected memory page dependent upon the output of the comparison) [STRONGIN’s Fig. 7-8, Fig. 10, Col.7, Line 33 to Col. 8, Line 17]; (receiving user equipment a base identifier value (a first identifier value) for computation of an identifier value and transmitting reply message after determining that computation based on the base value (the first identifier value) generates an identifier value (second identifier value)) [DECARREAU’s Par. 0028-0030; Par. 0094-0095; Par. 0112-0113]. . With respect to claims 4 and 18, STRONGIN and DECARREAU teach memory access method, wherein the first information further comprises a first permission value, and the first permission value indicates a first access permission of the second apparatus for the first physical address [memory management unit including a security check for a received physical address within a selected memory page, and security attributes of the selected memory page (STRONGIN’s Col. 3, Line 38 to Col. 4, Line 26)]; (the computed identifier value based on one or more input parameter values featuring security key value indicating access permission) [DECARREAU’s Par. 0094-0096]. With respect to claims 5 and 19, STRONGIN and DECARREAU teach memory access method, wherein the first information further comprises a granularity of physical address space, the granularity of the physical address space indicates a range of the physical address space, and the physical address space comprises the first physical address [memory management unit accesses the selected memory page dependent upon the output comparison, the address page featuring the physical address resulting from the physical address determined whether the access is authorized, (STRONGIN’s Col. 3, Line 38 to Col. 4, line26; Col.7, Line 33 to Col. 8, Line 17)]. With respect to claim 6, STRONGIN and DECARREAU teach memory access method, wherein the determining the access permission of the second apparatus for the first physical address based on the first security check value and the second security check value comprises: verifying the first security check value with the second security check value; and when the first security check value is verified successfully with the second security check value, determining that the access permission of the second apparatus for the first physical address is access permitted (security check unit receiving a physical address generated during execution of a current instruction, the physical address residing within a selected memory page, the security check unit to compare numerical value conveyed by a security attribute of the current instruction to a numerical value conveyed by the security attribute of the selected memory page to produce an output signal dependent upon a result of the comparison (STONGIN’s Fig. 7; Col. 7, Lines 33-65)]. Allowable Subject Matter Claims 7-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. WO 2022021446 A1 (LIU) teaching memory protection method and a protection proxy control apparatus, wherein: the protection proxy control apparatus can obtain, according to an identifier of a data flow of an accelerator or the IO device, permission information of a physical page table where a physical address requested by the data flow to access is located, and perform permission check on a memory access request according to the permission information. US 12107964 B2 (PUNAL et al) teaching method implementing technique performed by a miner and comprising: receiving a message, checking whether a security level indication associated with the message matches one of the one or more security levels configured for the miner to determine whether the miner is to participate in the computation of the block for the message, and starting to compute the block for the message if it is determined that the miner is to participate in the computation of the block for the message. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached at (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PIERRE MICHEL BATAILLE/ Primary Examiner, Art Unit 2136
Read full office action

Prosecution Timeline

Sep 29, 2024
Application Filed
Sep 17, 2025
Non-Final Rejection mailed — §103
Dec 17, 2025
Response Filed
Mar 19, 2026
Final Rejection mailed — §103
Jun 19, 2026
Response after Non-Final Action
Jul 20, 2026
Request for Continued Examination
Jul 22, 2026
Response after Non-Final Action
Sep 15, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+6.3%)
2y 4m (~3m remaining)
Median Time to Grant
High
PTA Risk
Based on 1216 resolved cases by this examiner. Grant probability derived from career allowance rate.

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