DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 09/30/2024.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 15-17 are objected to because of the following informalities:
Regarding independent claim 15, in L6, amend phrase “circuit,, wherein” to – “circuit, wherein”--.
Regarding claim 16, in L3, amend phrase “voltage threshold, ;” to – “ voltage threshold;”--.
Regarding claim 17, in L3, amend phrase “voltage threshold, .” to – “ voltage threshold.”--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 10 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 2, 10 and 16, in last line, Applicant claims, “the second voltage threshold is greater than or equal to the first voltage threshold”, which is indefinite. Applicant fails to clearly point out what is “the second voltage threshold” and its relationship to the switching on/off of the “controllable switch”. “a peak voltage of the DC current” and “a first voltage threshold”. Due to ambiguity and lack of clarity, under broadest reasonable interpretations (BRI), going forward Examiner is not considering role of “the second voltage threshold is greater than or equal to the first voltage threshold”, when rejecting following claim(s), under 103 Rejection.
Appropriate Correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-9, 12-15 and 18-20 are rejected under 35 U.S.C 103 as being unpatentable over George D. Blankenship (“Ref 612”, US Pat 6091612) in view of Telefus et al. (“Telefus”, US Pat 9660544).
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Above Fig. 15 is from Applicant’s own invention provided for comparison with following prior art(s)
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Above Fig annotated Fig. 1-4, from George D. Blankenship (“Ref 612”, US Pat 6091612)
Regarding independent claims 1, 9 and 15, Ref 612 teaches a power module (Fig. 1-4; col. 3 L19-col. 4 L65 and claims 1-27), comprising:
a rectifier circuit (full-bridge rectifier 14), configured to receive and rectify an alternating current (AC source 10), and output a direct current (full-bridge rectifier 14 includes D1-4, providing rectified DC output of AC source 10);
a valley-fill power factor correction circuit (20: forms using capacitors ‘C1-2, 212’, diodes ‘D5, 72’, BJT 202; wherein, C1, 72 and C2 form a series-connected charging loop; wherein, capacitance of C1 > C2; and diode D1 is a parasitic diode connected in parallel to FET) configured to adjust a power factor of the rectifier circuit (full-bridge rectifier 14 includes D1-4, providing rectified DC output of AC source 10), comprising a plurality of capacitors (C1-2) and a plurality of diodes (diodes ‘D5, 72’), wherein the plurality of capacitors (C1-2) and some diodes of the plurality of diodes (diodes ‘D5, 72’) form a series-connected charging loop (wherein, C1, 72 and C2 form a series-connected charging loop);
a controllable switch (D6 & BJT 202), connected between a reference capacitor (i.e., C1) of the plurality of capacitors (C1-2) and a reference ground (GND, via 212. Also, see period B &D in Fig. 3a-b & 4b) and…, wherein, when the controllable switch is turned on (i.e., 202=ON, resulting C1 connected to ground, via other diode operations in 20), the reference capacitor (i.e., C1) is connected to the reference ground (GND, via 212); and
a control circuit (204, Va) configured to control, depending on a type of the alternating current (+/-Vac of 10 with a range of 200-600 VAC), the controllable switch to be turned on or off (202 being on/off by ‘204, Va’), wherein the type of the alternating current is a high-voltage alternating current (Fig. 3a-b, 4b; period A) or a low-voltage alternating current (Fig. 3a-b, 4b; period C) depending on a peak voltage (Fig. 3a-b, 4b; +/- Vpeak during period A vs. C; claims 1-2, 4-5).
However, Ref 612 fails to teach the controllable switch, connected in parallel to a reference diode.
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Above annotated Fig. 1-2, from Telefus et al. (“Telefus”, US Pat 9660544)
However, Telefus teaches (Fig. 1-2; col. 2 L20-48) old and established use of interchangeable use between a diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and a controllable MOSFET or BJT transistor(s) (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and further be connected in parallel to a reference parasitic diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 612’s power module to replace one of the diodes (i.e., Ref 612’s D6 being replaced with FET) with a controllable switch (MOSFET or BJT), and further be connected in parallel to a reference parasitic diode, as disclosed by Telefus, as a selective circuit design choice, regardless of various power module or converter use, in addition to taught controllable switch, as doing so would have provided an improved steady, precise and synchronous rectification operation between the replaced element’s input and output, resulting to overall improved efficiency of switching rectification operation within the series connected charging loop, as taught by Telefus (col. 2 L20-23 and col. 1 L20-25).
[Additional NOTE:
Since, Applicant never claims any specific direct connection between valley-fill PFC’s included each capacitor (i.e., 1st-2nd end of each capacitor), diodes (i.e., each diode’s anode & cathode), FETs (i.e., source, drain and gate), leads to have each prior art teaching each and every element in the claims, under BRI. Applicant also never claim exactly from which output point this peak voltage of the DC current being considered from, as after rectifier’s output everything is DC output and based on diode & switching operation, max/min peak voltages are anticipated, leads to have each prior art teaching each and every element in the claims, under BRI yet again.
Examiner recommends to claim direct connection between each element and along with incorporation of comparing means (claims 2-3), Applicant may overcome this 103 Rejection. As always, a further search will be conducted, based on the amendment or arguments provided by Applicant’s on next filed response to this non-final rejection to determine allowability of the claims in the case.]
Regarding claims 4, 13, 18, Ref 612 teaches the valley-fill power factor correction circuit (20: forms using capacitors ‘C1-2, 212’, diodes ‘D5, 72’, BJT 202; wherein, C1, 72 and C2 form a series-connected charging loop; wherein, capacitance of C1 > C2; and diode D1 is a parasitic diode connected in parallel to FET) comprises a first capacitor (C1), a second capacitor (C2) (Capacitance of C1 > C2), …, a second diode (D5), and a third diode (diode 72), and the first capacitor, the third diode, and the second capacitor form a series-connected charging loop (C1, 72 and C2 form a series-connected charging loop).
However, Ref 612 fails to teach a first diode related to the controllable switch’s parallel connected parasitic reference diode.
However, Telefus teaches (Fig. 1-2; col. 2 L20-48) old and established use of interchangeable use between a diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and a controllable MOSFET or BJT transistor(s) (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and further be connected in parallel to a first reference parasitic diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 612’s power module to replace one of the diodes (i.e., Ref 612’s D6 being replaced with FET) with a controllable switch (MOSFET or BJT), and further be connected in parallel to a reference parasitic diode, as disclosed by Telefus, as a selective circuit design choice, regardless of various power module or converter use, in addition to taught controllable switch, as doing so would have provided an improved steady, precise and synchronous rectification operation between the replaced element’s input and output, resulting to overall improved efficiency of switching rectification operation within the series connected charging loop, as taught by Telefus (col. 2 L20-23 and col. 1 L20-25).
[See above Additional NOTE under claims 1, 9 and 15, which is applicable here.]
Regarding claim 5, 19, Ref 612 fails to teach the controllable switch is connected in parallel to the first diode.
However, Telefus teaches (Fig. 1-2; col. 2 L20-48) old and established use of interchangeable use between a diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and a controllable MOSFET or BJT transistor(s) (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and further be connected in parallel to a first reference parasitic diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 612’s power module to replace one of the diodes (i.e., Ref 612’s D6 being replaced with FET) with a controllable switch (MOSFET or BJT), and further be connected in parallel to a reference parasitic diode, as disclosed by Telefus, as a selective circuit design choice, regardless of various power module or converter use, in addition to taught controllable switch, as doing so would have provided an improved steady, precise and synchronous rectification operation between the replaced element’s input and output, resulting to overall improved efficiency of switching rectification operation within the series connected charging loop, as taught by Telefus (col. 2 L20-23 and col. 1 L20-25).
[See above Additional NOTE under claims 1, 9 and 15, which is applicable here.]
Regarding claims 6, 12, 20, Ref 612 fails to teach the controllable switch is a field-effect transistor.
However, Telefus teaches (Fig. 1-2; col. 2 L20-48) old and established use of interchangeable use between a diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and a controllable MOSFET or BJT transistor(s) (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and further be connected in parallel to a first reference parasitic diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 612’s power module to replace one of the diodes (i.e., Ref 612’s D6 being replaced with FET) with a controllable switch (MOSFET or BJT), and further be connected in parallel to a reference parasitic diode, as disclosed by Telefus, as a selective circuit design choice, regardless of various power module or converter use, in addition to taught controllable switch, as doing so would have provided an improved steady, precise and synchronous rectification operation between the replaced element’s input and output, resulting to overall improved efficiency of switching rectification operation within the series connected charging loop, as taught by Telefus (col. 2 L20-23 and col. 1 L20-25).
[See above Additional NOTE under claims 1, 9 and 15, which is applicable here.]
Regarding claims 7, 14, Ref 612 fails to teach the first diode is a parasitic diode of the field-effect transistor.
However, Telefus teaches (Fig. 1-2; col. 2 L20-48) old and established use of interchangeable use between a diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and a controllable MOSFET or BJT transistor(s) (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’) and further be connected in parallel to a first reference parasitic diode (Fig. 1; diode D1 being replaced with a BJT or FET, wherein Fig. 2 shows explicit use of a ‘FET Q2 and a reference parasitic diode D2’).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 612’s power module to replace one of the diodes (i.e., Ref 612’s D6 being replaced with FET) with a controllable switch (MOSFET or BJT), and further be connected in parallel to a reference parasitic diode, as disclosed by Telefus, as a selective circuit design choice, regardless of various power module or converter use, in addition to taught controllable switch, as doing so would have provided an improved steady, precise and synchronous rectification operation between the replaced element’s input and output, resulting to overall improved efficiency of switching rectification operation within the series connected charging loop, as taught by Telefus (col. 2 L20-23 and col. 1 L20-25).
[See above Additional NOTE under claims 1, 9 and 15, which is applicable here.]
Regarding claim 8, Ref 612 teaches a capacitance value of the first capacitor (C1’s capacitance value) and a capacitance value of the second capacitor (C2’s capacitance value), except that the first capacitor’s capacitance value being explicitly greater than or equal to the second capacitor’s a capacitance value.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 612’s the first capacitor’s capacitance value being explicitly greater than or equal to the second capacitor’s a capacitance value, as doing so would have provided a specific certain percentage of valley fill operation, as taught by Ref 612 (claims 1-2, 4), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, applicant has not disclosed any criticality for the claimed limitations.
Claims 2-3, 10-11, 16-17 are rejected under 35 U.S.C 103 as being unpatentable over Ref 612 (US Pat 6091612), in view of Telefus (US Pat 9660544) and Ge et al. (“Ge”, US Pat 9240711).
Regarding claims 2, 10, 16, Ref 612 teaches wherein the control circuit (204, Va) is further configured to turn on the controllable switch (202 being on/off by ‘204, Va’) in response …; and the second voltage threshold is greater than or equal to the first voltage threshold (this lined limitation is not considered, due to lack of clarity, indefiniteness and ambiguity; see above 112(b) rejection).
However, Ref 612 fails to teach the control circuit is further configured to turn on the controllable switch in response to a peak voltage of the direct current being less than a first voltage threshold.
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Above Fig. 9, from Ge et al. (“Ge”, US Pat 9240711)
However, Ge teaches (Fig. 8 or 9; col. 9 L40-col. 11 L40) the control circuit is further configured to turn on the controllable switch in response to a peak voltage of the direct current being less than a first voltage threshold (Vref) ( i.e., using control circuit 304-305, such that when peak & filtered/compensated DC voltage Vxi being superimposed with 309’s output and together fed to the inverting input of comparing means 310 to compare with Vref, causing S1 to be on or off, via 305, resulting any one of C2-4 connected to ground).
[Additional Examiner’s NOTE: Ge teaches (Fig. 8 or 9; col. 9 L40-col. 11 L40)
a valley-fill power factor correction circuit (valley-fill PFC) (combined operation of 303, 307, includes ‘capacitors C1-4, diodes D1-3, resistors ‘R6-7’ to adjust PFC of rectifier 302’s DC output; wherein, D2, C2 and D3 form a series-connected charging loop; wherein, under BRI, one in the ordinary skill in the could easily configured such that capacitance of C2 > C1);
a controllable switch (S1), connected between a reference capacitor (i.e., any one of C2-4) of the plurality of capacitors (C1-4) and a reference ground (GND) and wherein when the controllable switch (S1) is turned on (i.e., using control circuit 304-305, such that when peak & filtered/compensated DC voltage Vxi being superimposed with 309’s output and together fed to the inverting input of comparing means 310 to compare with Vref, causing S1 to be on or off, via 305, resulting any one of C2-4 connected to ground), the reference capacitor (i.e., any one of the capacitor C2-4) is connected to the reference ground (GND); and
a control circuit (304-305) configured to control (i.e., using control circuit 304-305, such that when peak & filtered/compensated DC voltage Vxi being superimposed with 309’s output and together fed to the inverting input of comparing means 310 to compare with Vref, causing S1 to be on or off, via 305, resulting any one of C2-4 connected to ground), depending on a type of the high or low voltage alternating current (+/-Vac), the controllable switch to be turned on or off (S1 being on or off), depending on a peak voltage (peak & filtered/compensated DC voltage Vxi being superimposed with 309’s output)].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 612 and Telefus’s collectively power module to further include a control circuit to control the combined operation of a valley-fill PFC and a controllable switch in such a way that the controllable switch is switched on in response to comparison between taught peak voltage of the direct current and a first voltage threshold, in order to have the taught reference capacitor being connected to the ground, as taught by Ge, as doing so would have provided a better total harmonic distortion control within the power module, as taught by Ge (abstract).
[See above Additional NOTE under claims 1, 9 and 15, which is applicable here.]
Regarding claims 3, 11, 17, Ref 612 teaches wherein the control circuit (204, Va) is further configured to turn on the controllable switch (202 being on/off by ‘204, Va’).
However, Ref 612 fails to teach the control circuit is further configured to turn off the controllable switch in response to that the peak voltage of the direct current being greater than the first voltage threshold.
However, Ge teaches (Fig. 8 or 9; col. 9 L40-col. 11 L40) the control circuit is further configured to turn off the controllable switch in response to that the peak voltage of the direct current being greater than the first voltage threshold (Vref) ( i.e., using control circuit 304-305, such that when peak & filtered/compensated DC voltage Vxi being superimposed with 309’s output and together fed to the inverting input of comparing means 310 to compare with Vref, causing S1 to be on or off, via 305, resulting any one of C2-4 connected to ground).
[Additional Examiner’s NOTE: Ge teaches (Fig. 8 or 9; col. 9 L40-col. 11 L40)
a valley-fill power factor correction circuit (valley-fill PFC) (combined operation of 303, 307, includes ‘capacitors C1-4, diodes D1-3, resistors ‘R6-7’ to adjust PFC of rectifier 302’s DC output; wherein, D2, C2 and D3 form a series-connected charging loop; wherein, under BRI, one in the ordinary skill in the could easily configured such that capacitance of C2 > C1);
a controllable switch (S1), connected between a reference capacitor (i.e., any one of C2-4) of the plurality of capacitors (C1-4) and a reference ground (GND) and wherein when the controllable switch (S1) is turned on (i.e., using control circuit 304-305, such that when peak & filtered/compensated DC voltage Vxi being superimposed with 309’s output and together fed to the inverting input of comparing means 310 to compare with Vref, causing S1 to be on or off, via 305, resulting any one of C2-4 connected to ground), the reference capacitor (i.e., any one of the capacitor C2-4) is connected to the reference ground (GND); and
a control circuit (304-305) configured to control (i.e., using control circuit 304-305, such that when peak & filtered/compensated DC voltage Vxi being superimposed with 309’s output and together fed to the inverting input of comparing means 310 to compare with Vref, causing S1 to be on or off, via 305, resulting any one of C2-4 connected to ground), depending on a type of the high or low voltage alternating current (+/-Vac), the controllable switch to be turned on or off (S1 being on or off), depending on a peak voltage (peak & filtered/compensated DC voltage Vxi being superimposed with 309’s output)].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ref 612 and Telefus’s collectively power module to further include a control circuit to control the combined operation of a valley-fill PFC and a controllable switch in such a way that the controllable switch is switched on in response to comparison between taught peak voltage of the direct current and a first voltage threshold, in order to have the taught reference capacitor being connected to the ground, as taught by Ge, as doing so would have provided a better total harmonic distortion control within the power module, as taught by Ge (abstract).
[See above Additional NOTE under claims 1, 9 and 15, which is applicable here.]
Conclusion
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
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