Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 30 September 2024 for application number 18/901,218. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 29 September 2023 (Provisional 63/586,833)
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 16 – 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 16 recites “a first memory level … configured to store one or more uncompressed pages that are most frequently or most recently accessed according to a recency list that tracks a plurality of uncompressed pages or compressed pages in the memory;
a second memory level of the at least two memory levels is configured to store one or more uncompressed pages that are frequently or recently accessed according to the recency list; and
the third memory level is configured to store one or more compressed pages that are least frequently or least recently accessed according to the recency list.” The metes and bounds are not clearly defined based on the “or” operator. It is unclear if the first, second, and third memory levels store frequently or recently accessed pages, and if they all store the same frequent/recent accessed-level amount of pages. Additionally, it is unclear if the recency list tracks uncompressed or compressed pages in the memory. Claims 17 – 20 depend from claim 16 and are rejected due to their dependency.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 7 – 12 and 18 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Claim 7 recites “the page is stored as a compressed page in the second memory level; and the processing circuit is further configured to decompress the compressed page into an uncompressed page and move the uncompressed page to a free page in the first memory level in response to an access of the page.” Examiner cannot locate in the specification where it recites the claim language, and respectfully requests attention brought to the section of the specification that recites the functionality where in response to a page access the compressed page is decompressed and moving the uncompressed page to a free page in the first memory level. Claims 8 – 12 depend from claim 7 and are rejected due to their dependency.
Claim 18 recites “the first length is 2 bits; and the second length is 8 bits.” Examiner respectfully requests attention brought to the section of the specification that recites the specific 8 bit length for the CTE second length.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 13, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Funk et al. [hereafter as Funk], US Pub. No. 2012/0084531 A1 in view of Tsirkin et al. [hereafter as Tsirkin], US Pub. No. 2022/0276889 A1.
As per claim 1, Funk discloses a computing system, comprising:
a memory comprising a plurality of memory levels [“Thus, Active Memory Expansion can be selectively enabled for one or more partitions of a system.”] [para. 0034]; and
a processing circuit configured to dynamically manage storage of data in the memory based on instructions received from an operating system (OS), wherein to dynamically manage storage of the data [“Once an acceptable or desired uncompressed memory space allocation is ascertained for a partition, the memory assigned to that partition of the processing system (as well as the other partitions of the system) can be dynamically set using, for example, Dynamic LPAR, available on POWER.RTM.-based servers, and supported by the AIX.RTM. and i/OS.TM. operating systems, offered by International Business Machines Corporation.”] [para. 0033], the processing circuit is further configured to:
determine a first memory level and a second memory level among the plurality of memory levels, the first memory level being used to store uncompressed pages and the second memory level being used to store compressed pages [“wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space”] [para. 0004];
determine free pages in the first memory level or the second memory level [“Once an acceptable or desired uncompressed memory space allocation is ascertained for a partition, the memory assigned to that partition of the processing system (as well as the other partitions of the system) can be dynamically set”] [para. 0033] [para. 0025]; and
store a page associated with the data in the first level or the second level based at least in part on the free [“collecting, by a processor, statistics on a rate at which pages are transferred between an uncompressed memory space and a compressed memory space of the partition's memory, wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space; adjusting size of the uncompressed memory space of the partition's memory; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resulting statistics in determining an acceptable memory allocation for the partition.”] [claim 1].
However, Funk does not explicitly disclose a free list; and
the free list.
Tsirkin teaches a free list [“the first set may be a list that identifies the available chunks”] [para. 0065]; and
the free list [“the first set may be a list that identifies the available chunks”] [para. 0065].
Funk and Tsirkin are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Funk with Tsirkin in order to modify Funk where “a free list; and the free list” as taught by Tsirkin. One of ordinary skill in the art would be motivated to combine Funk with Tsirkin before the effective filing date of the claimed invention to improve a system to “increase operational efficiencies. [Tsirkin, para. 0081].
Claim 15 is rejected with like reasoning as claim 1 above, except for the following remaining claim limitations:
determine at least two memory levels among the plurality of memory levels to store uncompressed pages and a third memory level among the plurality of memory levels to store compressed pages;
dynamically determine free pages in each of the at least two memory levels and the third memory level in real-time; and
store a page associated with the data in the at least two memory levels or the third memory level based at least in part on the free.
Funk discloses determine at least two memory levels [one or more partitions] among the plurality of memory levels to store uncompressed pages and a third memory level [one or more partitions] among the plurality of memory levels to store compressed pages [“Once an acceptable or desired uncompressed memory space allocation is ascertained for a partition, the memory assigned to that partition of the processing system (as well as the other partitions of the system) can be dynamically set using...”] [para. 0033] [“Thus, Active Memory Expansion can be selectively enabled for one or more partitions of a system.”] [para. 0034] [“wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space”] [para. 0004];
dynamically determine free pages in each of the at least two memory levels and the third memory level in real-time [“…memory assigned to that partition of the processing system (as well as the other partitions of the system) can be dynamically set...”] [para. 0033] [“Thus, Active Memory Expansion can be selectively enabled for one or more partitions of a system.”] [para. 0034]; and
store a page associated with the data in the at least two memory levels or the third memory level based at least in part on the free [“wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space; adjusting size of the uncompressed memory space of the partition's memory; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resulting statistics in determining an acceptable memory allocation for the partition.”] [para. 0003].
As per claim 2, Funk in view of Tsirkin discloses the computing system of claim 1, Funk discloses wherein the processing circuit is further configured to store the page associated with the data in the first memory level or the second memory level based further on a number of pages stored in the first memory level, a number of pages stored in the second memory level, or a number of pages stored in the first memory level and in the second memory level [“wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space; adjusting size of the uncompressed memory space of the partition's memory; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resulting statistics in determining an acceptable memory allocation for the partition.”] [para. 0003].
As per claim 13, Funk in view of Tsirkin discloses the computing system of claim 1, Tsirkin teaches wherein:
the free list in the first memory level comprises 4KB chunks [“In one example, the first set may be a list that identifies the available chunks that all have a first size (e.g., 4 KB)”] [para. 0065]; and
the free list in the second memory level comprises 4KB chunks and smaller sub-chunks within the 4KB chunks [“… the second set may be a list that identifies the available chunks that all have a second size (e.g., 2 MB).”] [para. 0065].
As per claim 14, Funk in view of Tsirkin discloses the computing system of claim 1, teaches Tsirkin wherein:
the processing circuit is a memory controller [“In one example, a processor may follow Von Neumann architectural model and may include an arithmetic logic unit (ALU), a control unit”] [para. 0020]; and
the memory is a dynamic random-access memory (DRAM) [Fig. 1, 104] separate from the memory controller [Fig. 1, 102] [“Physical memory 104 and storage device 106 may include any data storage that is capable of storing digital data. Physical memory 104 may include volatile memory devices (e.g., random access memory (RAM)), non-volatile memory devices (e.g., flash memory, NVRAM), and/or other types of memory devices.”] [para. 0021] [Examiner is interpreting other type of memory devices to include DRAM].
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claims 7 – 12 and 16 – 20 are rejected under a 112 rejection. Claim 1, 2, 13, 14, and 15 are rejected under a 103 rejection.
Allowable Subject Matter
Claims 3, 7, and 16 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(a) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims in independent form. Claims 4 – 6, 8 – 12, and 17 – 20 depend from claims 3, 7, and 16 and are objected to as considered containing allowable subject matter based on their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 3 the prior art of record, neither anticipates, nor renders obvious dynamically managing data storage by compressing a page table block, that is associated with a page, through embedding a compression translation entry to the page table block, and prefetching the compression translation entry during a page walk of serially fetching the compression translation entry after a page walk. Claims 4 – 6 depend from claim 3 and would be allowable based on their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 7 the prior art of record, neither anticipates, nor renders obvious storing a compressed page in the second memory level and decompressing the compressed page into an uncompressed page and moving the uncompressed page to a free page into the first memory level from the second memory level, all in response to an access of the page. Claims 8 – 12 depend from claim 7 and would be allowable based on their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 16 the prior art of record, neither anticipates, nor renders obvious first and second memory levels that stores uncompressed pages, third memory levels that stored compressed pages, where each level stores pages that are the most frequently accessed or most recently accessed based on a recency list that tracks uncompressed pages or compressed pages in memory. Claims 17 – 20 depend from claim 16 and would be allowable based on their dependency.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ramanujan et al., US Patent No. 9,418,700 B2 – teaches “According to one embodiment, controller logic 125 includes a free block list 220, which is implemented to select the replacement block location. Free block list 220 maintains a set of free PCM blocks that is continually filled to make up for block that have been retired for wear level or bad block move.” [col. 4, lines 30-35]
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/EW/Examiner, Art Unit 2135
/GAUTAM SAIN/Primary Examiner, Art Unit 2135