Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 17 September 2026 for application number 18/901,218. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1, 2, 9, 14, and 15 are currently amended.
Claim 7 is canceled.
Claims 1 – 6 and 8 – 20 are presented for examination.
Continued Prosecution Application
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 17 September 2026 has been entered.
Response to Amendment
Applicant’s amendment filed 17 September 2026 is sufficient to overcome the rejection of claims 1 – 6 and 8 – 20 based upon the currently amended independent claims and arguments.
Response to Arguments
Applicant’s arguments, filed 17 September 2026, with respect to the rejection(s) of claim(s) 1 – 6 and 8 – 20 under 35 USC § 103 have been fully considered and are persuasive based upon the currently amended independent claims and arguments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Soran et al., US Pub. No. 2012/0166725 A1 and Tringali, US Pub. No. 2024/0103758 A1.
Soran and Tringali, in combination with the prior art of record, reads on the claim limitations based on the current claim language. Please see the new grounds of rejection below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, 13, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Funk et al. [hereafter as Funk], US Pub. No. 2012/0084531 A1 in view of Soran et al. [hereafter as Soran], US Pub. No. 2012/0166725 A1 and further in view of Tringali [hereafter as Tringali], US Pub. No. 2024/0103758 A1.
As per claim 1, Funk discloses a computing system, comprising:
a memory comprising a plurality of memory levels [“Thus, Active Memory Expansion can be selectively enabled for one or more partitions of a system.”] [para. 0034]; and
a processing circuit configured to dynamically manage storage of data in the memory, wherein to dynamically manage storage of the data [“Once an acceptable or desired uncompressed memory space allocation is ascertained for a partition, the memory assigned to that partition of the processing system (as well as the other partitions of the system) can be dynamically set…”] [para. 0033], is further configured to:
determine a first memory level and a second memory level among the plurality of memory levels, the first memory level being used to store uncompressed pages and the second memory level being used to store compressed pages [“wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space”] [para. 0004];
determine free pages in the first memory level or the second memory level [“Once an acceptable or desired uncompressed memory space allocation is ascertained for a partition, the memory assigned to that partition of the processing system (as well as the other partitions of the system) can be dynamically set”] [para. 0033] [para. 0025]; and
store a page associated with the data in the first memory level or the second memory level based at least in part on the free [“collecting, by a processor, statistics on a rate at which pages are transferred between an uncompressed memory space and a compressed memory space of the partition's memory, wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space; adjusting size of the uncompressed memory space of the partition's memory; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resulting statistics in determining an acceptable memory allocation for the partition.”] [claim 1], wherein:
the page is stored as a compressed page in the second memory level [“wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space; adjusting size of the uncompressed memory space of the partition's memory; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resulting statistics in determining an acceptable memory allocation for the partition.”] [claim 1].
a free page in the first memory level [“Once an acceptable or desired uncompressed memory space allocation is ascertained for a partition, the memory assigned to that partition of the processing system (as well as the other partitions of the system) can be dynamically set”] [para. 0033] [para. 0025].
However, Funk does not explicitly disclose a processing circuit comprising a memory controller, the memory controller:
a free list; and
the free list; and
the memory controller is further configured to decompress the compressed page into an uncompressed page and move the uncompressed page to a free page in response to a memory request accessing the page; and
the free page is tracked by the free list.
Soran teaches a free list [“The data pages free list tracks the available pages on the volume.”] [para. 0134]; and
the free list [“The data pages free list tracks the available pages on the volume.”] [para. 0134];
further configured to decompress the compressed page into an uncompressed page in response to a memory request accessing the page [“The access may require the reading of the sub-allocation information to retrieve the location of the actual data. The compressed data may be read from the disk and decompressed on the processor.”] [para. 0246]; and
the free page is tracked by the free list [“The data pages free list tracks the available pages on the volume.”] [para . 0134].
Funk and Soran are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Funk with Soran in order to modify Funk where “a free list; and
the free list; and
further configured to decompress the compressed page into an uncompressed page in response to a memory request accessing the page; and
the free page is tracked by the free list” as taught by Soran. One of ordinary skill in the art would be motivated to combine Funk with Soran before the effective filing date of the claimed invention to improve a system “to satisfy the increasing demand of the storage space … significantly reduce the overall cost of the disk drives… the efficiency of the use of the drives is substantially improved.” [Soran, para. 0061].
However, Funk and Soran do not explicitly disclose a processing circuit comprising a memory controller, the memory controller:
the memory controller is further configured to uncompressed page and move the uncompressed page to a free page.
Tringali teaches the memory controller is further configured to uncompressed page and move the uncompressed page to a free page [“physical page 11 which was storing the uncompressed “cached” copy of host page 13 is moved to the free page list.”] [para. 0029] [“In an embodiment, buffer device 111 includes compression/decompression circuitry 112 (hereinafter, “compression circuitry 112”), access circuitry 113, and control circuitry 114. Access circuitry 113 is operatively coupled to memory devices 120. Access circuitry 113 is configured to access at least one of memory devices 120 to access allocated space 131, unallocated space 135, and node overhead space 139 stored by memory devices 120. In particular, access circuitry 113 is configured to access at least one of memory devices 120 to access allocated space 131 and unallocated space 135 to access uncompressed pages 141, compressed pages 149, and free pages 135a-135b. In an embodiment, buffer device 111 may be, or comprise, a processor running a real-time operating system that utilizes node overhead space 139.”] [para. 0016].
Funk, Soran, and Tringali are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Funk and Soran with Tringali in order to modify Funk and Soran where “the memory controller is further configured to uncompressed page and move the uncompressed page to a free page” as taught by Tringali. One of ordinary skill in the art would be motivated to combine Funk and Soran with Tringali before the effective filing date of the claimed invention to improve “memory space demands… physical page … which was storing the uncompressed “cached” copy of host page … is moved to the free page list.” [Tringali, para. 0029].
However, Funk, Soran, and Tringali do not explicitly disclose a processing circuit comprising a memory controller, the memory controller.
Tsirkin teaches a processing circuit comprising a memory controller, the memory controller [“In one example, a processor may follow Von Neumann architectural model and may include an arithmetic logic unit (ALU), a control unit”] [para. 0020].
Funk, Soran, Tringali, and Tsirkin are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Funk, Soran, and Tringali with Tsirkin in order to modify Funk, Soran, and Tringali for “a processing circuit comprising a memory controller, the memory controller” as taught by Tsirkin. One of ordinary skill in the art would be motivated to combine Funk, Soran, and Tringali with Tsirkin before the effective filing date of the claimed invention to improve a system to “increase operational efficiencies.” [Tsirkin, para. 0081].
Claim 15 is rejected with like reasoning as claim 1 above, except for the following remaining claim limitations:
determine at least two memory levels among the plurality of memory levels to store uncompressed pages and a third memory level among the plurality of memory levels to store compressed pages;
dynamically determine free pages in each of the at least two memory levels and the third memory level in real-time; and
store a page associated with the data in the at least two memory levels or the third memory level based at least in part on the free.
Funk discloses determine at least two memory levels [one or more partitions] among the plurality of memory levels to store uncompressed pages and a third memory level [one or more partitions] among the plurality of memory levels to store compressed pages [“Once an acceptable or desired uncompressed memory space allocation is ascertained for a partition, the memory assigned to that partition of the processing system (as well as the other partitions of the system) can be dynamically set using...”] [para. 0033] [“Thus, Active Memory Expansion can be selectively enabled for one or more partitions of a system.”] [para. 0034] [“wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space”] [para. 0004];
dynamically determine free pages in each of the at least two memory levels and the third memory level in real-time [“…memory assigned to that partition of the processing system (as well as the other partitions of the system) can be dynamically set...”] [para. 0033] [“Thus, Active Memory Expansion can be selectively enabled for one or more partitions of a system.”] [para. 0034]; and
store a page associated with the data in the at least two memory levels or the third memory level based at least in part on the free [“wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space; adjusting size of the uncompressed memory space of the partition's memory; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resulting statistics in determining an acceptable memory allocation for the partition.”] [para. 0003].
As per claim 2, Funk in view of Soran and further in view of Tringali discloses the computing system of claim 1, Funk discloses wherein the memory controller is further configured to store the page in the second memory level based further on a number of pages stored in the first memory level, a number of pages stored in the second memory level, or a number of pages stored in the first memory level and in the second memory level [“wherein uncompressed pages are stored in the uncompressed memory space and compressed pages are stored in the compressed memory space; adjusting size of the uncompressed memory space of the partition's memory; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resulting statistics in determining an acceptable memory allocation for the partition.”] [para. 0003].
As per claim 8, Funk in view of Soran and further in view of Tringali discloses the computing system of claim 1, Tsirkin teaches wherein a location of the free page is determined based on the free list [“Each of the chunks 218A-Z may be a contiguous or non-contiguous portion of memory that includes one or more memory units (e.g., blocks, pages).”] [para. 0029] [“the first set may be a list that identifies the available chunks”] [para. 0065].
As per claim 13, Funk in view of Soran and further in view of Tringali discloses the computing system of claim 1, Tsirkin teaches wherein:
the free list in the first memory level comprises 4KB chunks [“In one example, the first set may be a list that identifies the available chunks that all have a first size (e.g., 4 KB)”] [para. 0065]; and
the free list in the second memory level comprises 4KB chunks and smaller sub-chunks within the 4KB chunks [“… the second set may be a list that identifies the available chunks that all have a second size (e.g., 2 MB).”] [para. 0065].
As per claim 14, Funk in view of Soran and further in view of Tringali discloses the computing system of claim 1, Tsirkin teaches the memory is a dynamic random-access memory (DRAM) [Fig. 1, 104] separate from the memory controller [Fig. 1, 102] [“Physical memory 104 and storage device 106 may include any data storage that is capable of storing digital data. Physical memory 104 may include volatile memory devices (e.g., random access memory (RAM)), non-volatile memory devices (e.g., flash memory, NVRAM), and/or other types of memory devices.”] [para. 0021] [Examiner is interpreting other type of memory devices to include DRAM].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Funk et al. [hereafter as Funk], US Pub. No. 2012/0084531 A1 in view of Soran et al. [hereafter as Soran], US Pub. No. 2012/0166725 A1 and further in view of Tringali [hereafter as Tringali], US Pub. No. 2024/0103758 A1 and further in view of Tsirkin et al. [hereafter as Tsirkin], US Pub. No. 2022/0276889 A1 as applied to claim 1 above, and further in view of Chhabra et al. [hereafter as Chhabra], US Pub. No. 2016.0320972 A1.
As per claim 9, Funk in view of Soran and further in view of Tringali discloses the computing system of claim 1, however Funk, Soran, Tringali, and Tsirkin do not explicitly disclose wherein the memory request is associated with a last-level cache (LLC) miss or a translation lookaside buffer (TLB) miss.
Chhabra teaches wherein the access is associated with a last-level cache (LLC) miss or a translation lookaside buffer (TLB) miss [“… As indicated by block 504, one of tasks 108a-108f may initiate a page request. … A determination that a physical address is not present in the TLB is commonly referred to as a “TLB miss.” If it is determined that a TLB hit did not occur (i.e., a TLB miss occurred), it is then determined whether the physical address is present in a page table (not shown), as indicated by block 510.”] [para. 0046].
Funk, Soran, Tringali, Tsirkin, and Chhabra are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Funk, Soran, Tringali, and Tsirkin with Chhabra in order to modify Funk, Soran, Tringali, and Tsirkin “wherein the access is associated with a last-level cache (LLC) miss or a translation lookaside buffer (TLB) miss” as taught by Chhabra. One of ordinary skill in the art would be motivated to combine Funk, Soran, Tringali, and Tsirkin with Chhabra before the effective filing date of the claimed invention to improve a system “for adaptive compression-based demand paging…” and improve performance by “identifying … various tasks … and their respective latency tolerances and/or priorities. Such information may be determined empirically or in other ways… an ordered list of tasks …, ranked in order of latency tolerance and/or priority, … include a plurality of compression algorithms and compression block sizes and associate each group of one or more of the tasks … with a combination of compression algorithm and block size that achieves a latency tolerance and/or priority corresponding to the ranking.” [Chhabra, Abstract and para. 0045].
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 6 and 8 – 20 have received a first action on the merits and are subject of a first action non-final. Claims 1, 2, 8, 9, and 13 – 15 are rejected under a 103 rejection.
Allowable Subject Matter
Claims 3, 10, 11, 12, and 16 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten or amended to include all of the limitations of the base claim and any intervening claims in independent form. Claims 4 – 6 and 17 – 20 depend from claims 3 and 16 and are objected to as considered containing allowable subject matter based on their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 3 the prior art of record, neither anticipates, nor renders obvious dynamically managing data storage by compressing a page table block, that is associated with a page, through embedding a compression translation entry to the page table block, and prefetching the compression translation entry during a page walk of a serial fetching the compression translation entry after a page walk. Claims 4 – 6 depend from claim 3 and would be allowable based on their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 10 the prior art of record, neither anticipates, nor renders obvious updating a compression translation entry that is associated with a page after the page has been moved to a first memory level and upon a subsequent access of the uncompressed page by a page walker.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 11 the prior art of record, neither anticipates, nor renders obvious compressing an uncompressed page to a compressed page and moving the compressed page to a free page in a second memory level based on a recency list that tracks the compressed or uncompressed pages in memory. Claim 12 depends from claim 11 and would be allowable based on its dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 16 the prior art of record, neither anticipates, nor renders obvious first memory level that stores uncompressed pages with a highest access ranking, a second memory level that stores uncompressed pages with an intermediate access ranking, and third memory level that stored compressed pages with a lowest access ranking, where each level stores pages based on frequency of access or an access recency list. Claims 17 – 20 depend from claim 16 and would be allowable based on their dependency.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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/EW/Examiner, Art Unit 2135 /JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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