DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai et al (US PGPUB 2021/0075407) in view of Uemura et al (US PGPUB 2010/0308881).
Regarding claim 1, Figure 1 of Cai discloses a circuit comprising:
a first inverter having an output [1]
a first transmission gate having an input, an output, and an enable input [21]
wherein the input of the first transmission gate is coupled to the output of the first inverter [1 and 21]
a first latch having an input and an output, the input of the first latch coupled to the output of the first transmission gate [22 and 23]
a second latch having an input and an output, the input of the second latch coupled to the output of the first latch [32 and 33]
Cai does not explicitly disclose a second transmission gate having an input and an output, the input of the second transmission gate coupled to the second latch and the output of the second transmission gate coupled to the input of the first latch.
Figure 4 of Uemura discloses a second transmission gate having an input and an output [SW3], the input of the second transmission gate coupled to the second latch [107 and 108] and the output of the second transmission gate coupled to the input of the first latch [103 and 104].
Accordingly, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to have included a feedback transmission gate as taught by Uemura in the circuit of Cai for the purpose of reducing soft error, as implied by Uemura [paragraph 45].
Regarding claim 2, the combination of Cai and Uemura, as applied to claim 1, discloses wherein the enable input of the first transmission gate is configured to receive a first enable signal, and wherein an enable input of the second transmission gate is configured to receive the first enable signal [clk Figure 4 Uemura].
Regarding claim 3, the combination of Cai and Uemura, as applied to claim 1, discloses a third transmission gate having an input and an output, wherein the input of the third transmission gate is coupled to the output of the second latch, and wherein the output of the third transmission gate is coupled to the input of the second latch [33 Figure 1 Cai; well-known circuit design of a clock enabled inverter].
Regarding claim 4, the combination of Cai and Uemura, as applied to claim 3, discloses wherein the second latch comprises a second inverter and a third inverter cross-coupled with the second inverter [32 and 33 Figure 1 Cai].
Regarding claim 5, the combination of Cai and Uemura, as applied to claim 4, discloses wherein the input of the third transmission gate is coupled to an output of the third inverter [see rejection of claim 3].
Regarding claim 6, the combination of Cai and Uemura, as applied to claim 3, does not explicitly disclose a fourth transmission gate having an input and an output, wherein the input of the fourth transmission gate is coupled to the output of the first transmission gate, and wherein the output of the fourth transmission gate is coupled to the input of the first latch.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of the combination of Cai and Uemura, as applied to claim 3, by using two transmission gates at the input of the circuit where one of the transmission gates is used to enable the circuit, since it was well-known in the art to include an enable transmission gate on the input of a circuit to control enablement of the circuit.
Regarding claim 7, the combination of Cai and Uemura, as applied to claim 6, discloses wherein the third transmission gate comprises an enable input configured to receive a first clock signal, and wherein the fourth transmission gate comprises an enable input configured to receive the first clock signal [see rejection of claim 6].
Regarding claim 8, the combination of Cai and Uemura, as applied to claim 1, discloses wherein the first latch comprises: a first tri-state inverter having an input and an output, the input of the first tri-state inverter coupled to the output of the first latch, and the output of the first tri-state inverter is coupled to the input of the first latch; and a second inverter having an input and an output, the input of the second inverter coupled to the input of the first latch, and the output of the second inverter coupled to the output of the first latch [Figure 1 Cai].
Regarding claim 9, the combination of Cai and Uemura, as applied to claim 8, discloses a second tri-state inverter having an input, an output, and an enable input, the input of the second tri-state inverter coupled to the output of the second inverter, the output of the second tri-state inverter coupled to the input of the second latch, and the enable input of the second tri-state inverter configured to receive a clock signal, wherein an enable input of the first tri-state inverter is configured to receive the clock signal [Figure 1 Cai].
Regarding claim 11, the combination of Cai and Uemura, as applied to claim 1, discloses an output terminal coupled to the output of the second latch [ND Figure 4 Uemura].
Regarding claim 12, the combination of Cai and Uemura, as applied to claim 1, discloses an output terminal; and a second inverter having an input coupled to the output of the first latch, and an output coupled to the output terminal [109, ND, and Dout Figure 4 Uemura].
Allowable Subject Matter
Claims 10 and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19 and 20 are allowed.
Response to Arguments
Applicant's arguments filed 05/18/2026 have been fully considered but they are not persuasive.
Applicant argues that the combination of Cai and Uemura does not disclose the claimed invention of claim 1. The examiner disagrees. The applicant has not explicitly pointed to any part of the prior art combination that does not teach the claim limitations, and it should be clear from the current rejection that the combination of Cai and Uemura teaches all of the claim limitations, including the newly amended claim limitations. Therefore, the combination of Cai and Uemura teaches the claimed invention. Thus, the applicant’s arguments are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TOMI SKIBINSKI/Primary Examiner, Art Unit 2836
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