Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 7-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe (US Pub. No. 2016/0293742 A1).
As to claim 1, Watanabe discloses a semiconductor device (fig 2, device 1) comprising:
a support substrate (fig 2, 2);
a bonding layer (3) including a first metal region (13/14; [0036]) on at least a portion of an upper surface of the support substrate (2);
an underlying layer (25) on the bonding layer (3), the underlying layer (25) including a sub-collector region (25; [0038]) including a conductive semiconductor material ([0038]) and electrically connected to the first metal region (13);
a first transistor ([0033]) on the sub-collector region (25), the first transistor including a collector layer (26) electrically connected to the sub-collector region (25), a base layer (22) on the collector layer (25), and an emitter layer (23) on the base layer (22); and
a collector electrode (5) on the sub-collector region (25), the collector electrode (5) being outward of the first transistor to overlap the first metal region in plan view (metal region 13/14), and the collector electrode (5) being electrically connected to the sub-collector region (25).
As to claim 2, Watanabe discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the first metal region includes at least one metal selected from the group consisting of Au, Ag, Pt, Cu, Al, W, Ti, and Ta ([0056]).
As to claim 3, Watanabe discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the first metal region (13/14) includes a first lower metal region (13) closer to the support substrate (2) and a first upper metal region (14) closer to the underlying layer (25), and the first lower metal region and the first upper metal region are adhered to each other ([0056]).
As to claim 4, Watanabe discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the support substrate (2) includes a semiconductor material ([0034]) having a thermal conductivity higher than a thermal conductivity of a semiconductor material that configures the collector layer, the base layer, and the emitter layer of the first transistor and a thermal conductivity of the semiconductor material that configures the sub-collector region ([0034]).
As to claim 5, Watanabe discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the bonding layer further includes at least one second metal region electrically isolated from the first metal region (fig 22B, bonding layer 3 including first metal region corresponding to stack 4 and one second metal region corresponding to 91).
As to claim 7, Watanabe discloses the semiconductor device according to claim 5 (paragraphs above),
an insulating region (8A) between the first metal region (region corresponding to stack 4) and the second metal region (region corresponding to 91) in plan view, the insulating region including an oxide or a nitride ([0087]).
As to claim 8, Watanabe discloses the semiconductor device according to claim 5 (paragraphs above),
wherein a void is between the first metal region and the second metal region in plan view (fig 22A, void between first and second metal regions).
As to claim 9, Watanabe discloses the semiconductor device according to claim 2 (paragraphs above),
wherein the first metal region (13/14) includes a first lower metal region (13) closer to the support substrate (2) and a first upper metal region (14) closer to the underlying layer (25), and the first lower metal region and the first upper metal region are adhered to each other ([0056]).
As to claim 10, Watanabe discloses the semiconductor device according to claim 2 (paragraphs above),
wherein the support substrate (2) includes a semiconductor material ([0034]) having a thermal conductivity higher than a thermal conductivity of a semiconductor material that configures the collector layer, the base layer, and the emitter layer of the first transistor and a thermal conductivity of the semiconductor material that configures the sub-collector region ([0034]).
As to claim 11, Watanabe discloses the semiconductor device according to claim 3 (paragraphs above),
wherein the support substrate (2) includes a semiconductor material ([0034]) having a thermal conductivity higher than a thermal conductivity of a semiconductor material that configures the collector layer, the base layer, and the emitter layer of the first transistor and a thermal conductivity of the semiconductor material that configures the sub-collector region ([0034]).
As to claim 12, Watanabe discloses the semiconductor device according to claim 9 (paragraphs above),
wherein the support substrate (2) includes a semiconductor material ([0034]) having a thermal conductivity higher than a thermal conductivity of a semiconductor material that configures the collector layer, the base layer, and the emitter layer of the first transistor and a thermal conductivity of the semiconductor material that configures the sub-collector region ([0034]).
As to claim 13, Watanabe discloses the semiconductor device according to claim 2 (paragraphs above),
wherein the bonding layer further includes at least one second metal region electrically isolated from the first metal region (fig 22B, bonding layer 3 including first metal region corresponding to stack 4 and one second metal region corresponding to 91).
As to claim 14, Watanabe discloses the semiconductor device according to claim 3 (paragraphs above),
wherein the bonding layer further includes at least one second metal region electrically isolated from the first metal region (fig 22B, bonding layer 3 including first metal region corresponding to stack 4 and one second metal region corresponding to 91).
As to claim 15, Watanabe discloses the semiconductor device according to claim 4 (paragraphs above),
wherein the bonding layer further includes at least one second metal region electrically isolated from the first metal region (fig 22B, bonding layer 3 including first metal region corresponding to stack 4 and one second metal region corresponding to 91).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe in view of Umemoto et al. (US Pub. No. 2021/0098585 A1), hereafter referred to as Umemoto.
As to claim 6, Watanabe discloses the semiconductor device according to claim 5 (paragraphs above).
wherein the underlying layer further includes an insulating element isolation region (8A) outward of the sub-collector region (25) in plan view.
However, Watanabe does not disclose the semiconductor device further comprises:
a passive element on an element isolation region and not overlapping the first metal region or the second metal region in plan view.
Nonetheless, Umemoto discloses a semiconductor device (figs 3-4; [0056]) comprising a similar HBT (30; [0058]) and a passive element (65; [0060]) on an element isolation region (22; [0043]) and not overlapping a sub-collector region (21; [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the passive element over an element isolation region in the semiconductor device of Watanabe as taught by Umemoto since this will improve the integrated circuit performance of the semiconductor device as incorporated in an amplifier circuit.
As to claim 16, Watanabe discloses the semiconductor device according to claim 13 (paragraphs above).
wherein the underlying layer further includes an insulating element isolation region (8A) outward of the sub-collector region (25) in plan view.
However, Watanabe does not disclose the semiconductor device further comprises:
a passive element on an element isolation region and not overlapping the first metal region or the second metal region in plan view.
Nonetheless, Umemoto discloses a semiconductor device (figs 3-4; [0056]) comprising a similar HBT (30; [0058]) and a passive element (65; [0060]) on an element isolation region (22; [0043]) and not overlapping a sub-collector region (21; [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the passive element over an element isolation region in the semiconductor device of Watanabe as taught by Umemoto since this will improve the integrated circuit performance of the semiconductor device as incorporated in an amplifier circuit.
As to claim 17, Watanabe discloses the semiconductor device according to claim 14 (paragraphs above).
wherein the underlying layer further includes an insulating element isolation region (8A) outward of the sub-collector region (25) in plan view.
However, Watanabe does not disclose the semiconductor device further comprises:
a passive element on an element isolation region and not overlapping the first metal region or the second metal region in plan view.
Nonetheless, Umemoto discloses a semiconductor device (figs 3-4; [0056]) comprising a similar HBT (30; [0058]) and a passive element (65; [0060]) on an element isolation region (22; [0043]) and not overlapping a sub-collector region (21; [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the passive element over an element isolation region in the semiconductor device of Watanabe as taught by Umemoto since this will improve the integrated circuit performance of the semiconductor device as incorporated in an amplifier circuit.
As to claim 18, Watanabe discloses the semiconductor device according to claim 15 (paragraphs above).
wherein the underlying layer further includes an insulating element isolation region (8A) outward of the sub-collector region (25) in plan view.
However, Watanabe does not disclose the semiconductor device further comprises:
a passive element on an element isolation region and not overlapping the first metal region or the second metal region in plan view.
Nonetheless, Umemoto discloses a semiconductor device (figs 3-4; [0056]) comprising a similar HBT (30; [0058]) and a passive element (65; [0060]) on an element isolation region (22; [0043]) and not overlapping a sub-collector region (21; [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the passive element over an element isolation region in the semiconductor device of Watanabe as taught by Umemoto since this will improve the integrated circuit performance of the semiconductor device as incorporated in an amplifier circuit.
As to claim 19, Watanabe in view of Umemoto disclose the semiconductor device according to claim 6 (paragraphs above).
Watanabe further discloses an insulating region (8A) between the first metal region (region corresponding to stack 4) and the second metal region (region corresponding to 91) in plan view, the insulating region including an oxide or a nitride ([0087]).
As to claim 20, Watanabe in view of Umemoto disclose the semiconductor device according to claim 6 (paragraphs above).
Watanabe further discloses wherein a void is between the first metal region and the second metal region in plan view (fig 22A, void between first and second metal regions).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2010/0187571 A1 and US Pub. No. 2019/0326191A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 9/24/2026
