DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-9 are presented for examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d) which papers have been placed of record in the file.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is accepted.
Drawings
The formal drawings are accepted.
Claim Rejections - 35 USC § 101
35. U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 7-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
At step 1, the independent claim 7 recites receiving channel values read and performing a decoding process on the channel values in an iterative manner according to a parity check matrix of a quasi-cyclic low-density parity-check (QC-LDPC) code, and therefore is a process, which is a statutory category of invention.
At step 2A, prong one, the claim recites method in which calculating a first shift parameter based on a shift parameter matrix, wherein the first shift parameter is a difference between a specific first column and a specific second column of the shift parameter matrix; updating the plurality of Q messages based on the channel values and the plurality of R messages; and performing circular shift on the plurality of Q messages to generate a plurality of Q' messages according to the first shift parameter. Thus, limitation (b) recites a concept that falls into the “mathematical concepts” (for example a mathematical relationship or formula) group of abstract ideas and the claim is directed to judiciary exception.
At step 2A, prong two, this judicial exception is not integrated into a practical application. The claim recites the additional elements “the shift parameter matrix is initiated with a base matrix corresponding to the parity check matrix, and a circular shift of one column is applied to the shift parameter matrix and the limitation are also not indicative of integration into a practical application because they amount no more than extra-solution activity that is not directly linked to the abstract idea. Further, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
At step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the claims are directed to an abstract mathematical concepts such as calculating a shift parameter based on a shift parameter matrix and updating messages based on channel values and performing circular shift on the messages and the use of a general-purpose computer is insufficient to raise the abstract algorithm to the level of a practical application. In addition to the discussion above with respect to integration of the abstract idea into a practical application, the additional elements of the claim amount to no more than linking the abstract idea to a field of use and performing well-understood, routine and conventional extra-solution activities. Additionally, the elements of “flash memory and “memory controller” merely apply the exception using generic components, which cannot provide an inventive concept. The claim is not patent eligible.
Dependent claims 8 and 9 do not add anything significantly more to independent claim 7 and therefore are rejected as well.
Allowable Subject Matter
Claims 1-6 are allowed. The following is an Examiner's statement of reasons for allowance:
Independent claim 1 of the present application teaches, for example, “A flash memory controller for accessing a flash memory, comprising: a first memory for storing a program code; a microprocessor for executing the program code to control access to the flash memory; and a decoder for receiving channel values read from the flash memory and performing a decoding process of a quasi-cyclic low-density parity-check (QC-LDPC) code, wherein the decoding process of the decoder involves a plurality of Q messages and a plurality of R messages, and the decoder comprises: a shift parameter unit for generating a first shift parameter and a second shift parameter based on a X×Y base matrix of the QC-LDPC code; a second memory for storing the plurality of Q messages; a third memory for storing the plurality of R messages; a variable node block for updating the plurality of Q messages based on the channel values read from the flash memory and the plurality of R messages; a first shift block for generating a plurality of Q messages based on the plurality of Q messages and the first shift parameter; a second shift block for generating a plurality of status data S'; and a check node block for updating the plurality of R messages and outputting a plurality of status data S based on the plurality of Q' messages and the plurality of status data S', wherein each status data S comprises a minimum value, a second minimum value, an index of the minimum value, and a global sign value; wherein the second shift block receives the plurality of status data S and performs circular shift according to the second shift parameter to generate the plurality of status data S'.
The prior arts of record including the IDS filed by the applicant taken singly or incombination fail to teach, anticipate, suggest, or render obvious the foregoing limitations, “a first memory for storing a program code; a microprocessor for executing the program code to control access to the flash memory; and a decoder for receiving channel values read from the flash memory and performing a decoding process of a quasi-cyclic low-density parity-check (QC-LDPC) code, wherein the decoding process of the decoder involves a plurality of Q messages and a plurality of R messages, and the decoder comprises: a shift parameter unit for generating a first shift parameter and a second shift parameter based on a X×Y base matrix of the QC-LDPC code; a second memory for storing the plurality of Q messages; a third memory for storing the plurality of R messages; a variable node block for updating the plurality of Q messages based on the channel values read from the flash memory and the plurality of R messages; a first shift block for generating a plurality of Q messages based on the plurality of Q messages and the first shift parameter; a second shift block for generating a plurality of status data S'; and a check node block for updating the plurality of R messages and outputting a plurality of status data S based on the plurality of Q' messages and the plurality of status data S', wherein each status data S comprises a minimum value, a second minimum value, an index of the minimum value, and a global sign value; wherein the second shift block receives the plurality of status data S and performs circular shift according to the second shift parameter to generate the plurality of status data S'”. Consequently, claim 1 is allowed over the prior arts.
Dependent claims 2-6 depend from allowable independent claims and inherently include limitations therein and therefore are allowed as well.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hsu et al. (U.S. PN: 11,316,532) describe a method for improving decoding operations of a decoder is described. The method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising N columns, wherein N is a positive integer, wherein each of at least B columns of the parity matrix has a column weight that exceeds a predetermined column weight.
Asadi et al. (U.S. PN: 11,206,043) teach a method for reducing complexity of a bit-flipping decoder for QC-LDPC codes includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular quasi-cyclic low-density parity-check (QC-LDPC) code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword
Ryabinin et al. (U.S. PN: 10,565,040) describe the decoder 152 may be configured to process the representation of the codeword based on the QC-LDPC parity check matrix 142 that has a first block matrix size according to the decoding mode (e.g., a first matrix size for the ULP mode). The reordering circuit 166 may be further configured to selectively reorder the decoding messages in the reduced-power configuration associated with the decoding mode to transform the QC-LDPC parity check matrix to a second QC-LDPC parity check matrix having a second block matrix size smaller than the first block matrix size.
Rad (U.S. PN: 9,548,759) teaches a QC-LPDC code's quasi-cyclic parity check matrix 701 in a shift representation and a bi-partite graph illustrating the use of parallel processing in the layered approach used to decode the QC-LDPC code in accordance with some embodiments. Graph 700 includes grouped check nodes 721, 722 and 723 and grouped variable nodes 711, 712, 713, 714, 715, and 716. The edges between the grouped check nodes and the grouped variable nodes may represent possible permutations, π.sub.i, of a plurality of edges generated based on a non-zero circulant in quasi-cyclic parity check matrix 701. In other words, the non-zero circulant may be the adjacency matrix of the sub-graph of connections between each group of check nodes and each group of variable nodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/ Primary Examiner,
Art Unit 2112