DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Claim Status
Claims 1-20 are currently pending. Claims 1 are amended as per Applicant’s amendment filed on 27 February 2026.
Response to Arguments
Examiner withdraws the 112 rejections in favor of the amended claims.
Applicant's arguments filed 27 February 2026 have been fully considered but they are not persuasive.
With regards to Applicant’s arguments on pages 7-9, in essence, “Applicant respectfully submits that Inbar fails to teach or suggest both program passes originating from the same program buffer, regardless of how Inbar's components are mapped to the claimed elements. This deficiency can be demonstrated by analyzing Inbar under two possible interpretations.”. This has not been found persuasive. Inbar teaches performing the fine write and foggy write using the same buffer ([Inbar abstract, 0007-0008, 0031, Fig. 1]). Examiner suggests Applicant amend the claims to further distinguish the claims along what has been argued and what is supported by the specification.
The prior art rejections are maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inbar (US 20220076735 A1) in view of Muchherla (US 20200133585 A1).
Referring to claims 1, 8, and 15, taking claim 1 as exemplary, Inbar teaches
A memory sub-system comprising: a memory device comprising a first portion configured as a program buffer and a second portion configured as primary memory; ([Inbar abstract, 0026-0027, Fig. 1] The data storage device 104 communicates with the host device 102 through an interface 106 included in the data storage device 104. The data storage device 104 includes a controller 108, a buffer 114, and one or more memory devices 110. Data storage device 104 includes a buffer 114 which is a region of physical memory storage used to temporarily store data while it is being moved from one place to another (i.e., from host device 102 to data storage device 104). The data will then pass through the buffer 114 of the data storage device 104 and be stored in the memory device 110. If the data is written to a SLC memory, then the data is simply written. If, however, the data is written to a MLC, such as a QLC memory, then a foggy-fine writing process occurs.) a processing device, operatively coupled with the memory device, to perform operations comprising: ([Inbar 0022, 0032, Fig. 1] host device 102 includes any device having a processing unit or any form of hardware capable of processing data, including a general purpose processing unit, dedicated hardware (such as an application specific integrated circuit (ASIC)), configurable hardware such as a field programmable gate array (FPGA), or any other form of processing unit configured by software instructions, microcode, or firmware. The SLC 202 and QLC 206 zones may be implemented in different channels/dies.) initiating an initial program pass of first host data from the program buffer to the primary memory; ([Inbar abstract, 0026-0027, Fig. 1] The data will then pass through the buffer 114 of the data storage device 104 and be stored in the memory device 110. If the data is written to a SLC memory, then the data is simply written. If, however, the data is written to a MLC, such as a QLC memory, then a foggy-fine writing process occurs.) determining that the first host data is to be evicted from the program buffer; ([Inbar abstract 0021, 0032Fig. 3] Once the foggy write to MLC has completed, and the writing to SLC has also completed, the data buffer can be released.) and initiating a final program pass of the first host data from the program buffer to the primary memory ([Inbar abstract, 0021, 0029-0030, claim 1, Fig. 2B] The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to MLC with the data read from SLC and then a fine write to MLC with data re-read from SLC, the foggy write to MLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to MLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to MLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough. It is to be understood that while QLC has been described, the embodiments herein are applicable to multilevel cells (MLCs) including TLCs and QLCs.).
Inbar does not explicitly disclose determining that an amount of host data in the program buffer satisfies a buffer threshold criterion. Inbar does disclose buffer space and capacity limitations ([Inbar 0004-0005]).
Muchherla teaches determining that an amount of host data in the program buffer satisfies a buffer threshold criterion; ([Muchherla abstract, 0038, 0049-0053, claim 3, Figs. 5A, 5B] determine whether an amount of data written to the memory component satisfies a second threshold criterion pertaining to a data threshold, wherein identifying the first data block of the plurality of data blocks in the first portion of the memory component is in response to determining that the amount of data written to the memory component satisfies the second threshold criterion).
Inbar and Muchherla are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Inbar and Muchherla before him or her to modify the system of Inbar to include the threshold criterion of Muchherla, thereafter the system is connected to threshold criterion. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system have more adjustable triggering condition for management and movement of data as suggested by Muchherla. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Inbar with Muchherla to obtain the invention as specified in the instant application claims.
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 2, 9, and 16, taking claim 2 as exemplary, Inbar in view of Muchherla teaches
The memory sub-system of claim 1, wherein the processing device is to perform operations further comprising: receiving the first host data to be programmed to the memory device; and initiating a program of the first host data to the program buffer ([Inbar 0030] The host DRAM 112 passes data through the buffer 114. The data is read from the buffer 114 and is written in parallel to SLC 202 and QLC 206. The initial write to QLC 206 from buffer 114 is the Foggy step. Data is read from the SLC 202 and is passed through the relocation buffer 204 to the QLC 206. The write to QLC 206 from SLC 202 is the Fine step.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 3, 10, and 17, taking claim 3 as exemplary, Inbar in view of Muchherla teaches
The memory sub-system of claim 1, wherein the processing device is to perform operations further comprising: responsive to completing the final program pass of the first host data to the primary memory, evicting the first host data from the program buffer ([Inbar 0021] The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to MLC with the data read from SLC and then a fine write to MLC with data re-read from SLC, the foggy write to MLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to MLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to MLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough. It is to be understood that while QLC has been described, the embodiments herein are applicable to multilevel cells (MLCs) including TLCs and QLCs.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 4, 11, and 18, taking claim 4 as exemplary, Inbar in view of Muchherla teaches
The memory sub-system of claim 1, wherein the threshold criterion is configurable based on an overwrite rate of the host data in the program buffer ([Muchherla abstract, 0034-0035, 0038, 0049-0053, claim 3, Figs. 5A, 5B] determine whether an amount of data written to the memory component satisfies a second threshold criterion pertaining to a data threshold, wherein identifying the first data block of the plurality of data blocks in the first portion of the memory component is in response to determining that the amount of data written to the memory component satisfies the second threshold criterion. the triggering condition can be an amount of data written to the memory component exceeding a data threshold. FIG. 5A is an illustration of a memory sub-system 500 determining to relocate subsequent data based on a number of programming operations performed on a memory component. FIG. 5B is an illustration of a memory sub-system 550 determining to relocate subsequent data based on a number of programming operations performed on a memory component.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
The same motivation that was utilized for combining Inbar and Muchherla as set forth in claim(s) 1, 8, and 15 is equally applicable to this/these claim(s).
Referring to claims 5 and 12 taking claim 5 as exemplary, Inbar in view of Muchherla teaches
The memory sub-system of claim 1, wherein the first portion of the memory device configured as the program buffer comprises a set of memory cells configured as single-level cell (SLC) memory or multi-level cell (MLC) memory ([Inbar 0021, claim 1, Fig. 2B] one or more memory devices, the one or more memory devices including SLC memory and MLC memory).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 6 and 13, taking claim 6 as exemplary, Inbar in view of Muchherla teaches
The memory sub-system of claim 1, wherein the second portion of the memory device configured as the primary memory comprises a set of memory cells configured as tri-level cell (TLC) memory or quad-level cell (QLC) memory ([Inbar claims 1, 9, Fig. 2B] It is to be understood that while QLC has been described, the embodiments herein are applicable to multilevel cells (MLCs) including TLCs and QLCs).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 7, 14, and 20, taking claim 7 as exemplary, Inbar in view of Muchherla teaches
The memory sub-system of claim 1, wherein the initial program pass comprises coarsely programming memory cells in the primary memory to initial values representing a plurality of pages of the first host data, and wherein the final program pass comprises finely programming the memory cells in the primary memory to final values representing the plurality of pages of the first host data ([Inbar 0021, 0029-0030, claim 1, Fig. 2B] The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to MLC with the data read from SLC and then a fine write to MLC with data re-read from SLC, the foggy write to MLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to MLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to MLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough. It is to be understood that while QLC has been described, the embodiments herein are applicable to multilevel cells (MLCs) including TLCs and QLCs. FIG. 2B is a schematic illustration of a foggy-fine writing process. the schematic illustration of FIG. 2B executes the QLC foggy write in parallel to SLC programming step. The process utilizes the same resources and buffers which reduces the amount of NAND load transfers (from 5 to 4) and DRAM load transfers (from 4 to 2). The host DRAM 112 passes data through the buffer 114. The data is read from the buffer 114 and is written in parallel to SLC 202 and QLC 206. The initial write to QLC 206 from buffer 114 is the Foggy step. Data is read from the SLC 202 and is passed through the relocation buffer 204 to the QLC 206. The write to QLC 206 from SLC 202 is the Fine step.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claim 19, Inbar in view of Muchherla teaches
The non-transitory computer-readable storage medium of claim 15, wherein the first portion of the memory device configured as the program buffer comprises a set of memory cells configured as single-level cell (SLC) memory, ([Inbar 0021, claim 1, Fig. 2B] one or more memory devices, the one or more memory devices including SLC memory and MLC memory) and wherein the second portion of the memory device configured as the primary memory comprises a set of memory cells configured as quad-level cell (QLC) memory ([Inbar claims 1, 9, Fig. 2B] It is to be understood that while QLC has been described, the embodiments herein are applicable to multilevel cells (MLCs) including TLCs and QLCs).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Regarding foggy fine programming and buffers.
US 20210158874 A1
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132